13 lines
608 B
Tcl
13 lines
608 B
Tcl
## Genesys2 JA GPS RF input. JA pins are 3.3 V LVCMOS33.
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## JA[0] is MRCC and is the 16.367981 MHz RF/GPS-PLL reference clock.
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set_property PACKAGE_PIN U27 [get_ports rf_clk_pmod]
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set_property IOSTANDARD LVCMOS33 [get_ports rf_clk_pmod]
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create_clock -period 61.095 -name pmod_rf_clk [get_ports rf_clk_pmod]
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set_property PACKAGE_PIN U28 [get_ports {rf_data_pmod[0]}]
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set_property PACKAGE_PIN T26 [get_ports {rf_data_pmod[1]}]
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set_property PACKAGE_PIN T27 [get_ports {rf_data_pmod[2]}]
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set_property PACKAGE_PIN T22 [get_ports {rf_data_pmod[3]}]
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set_property IOSTANDARD LVCMOS33 [get_ports {rf_data_pmod[*]}]
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