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gps/hardware/fpga/genesys2/constraints/genesys2_pmod_spi.xdc
T
2026-07-12 11:01:51 +03:00

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## Genesys2 user SPI on PMOD JC. JA is used by GPS RF in RF_INPUT_MODE=pmod,
## and JB[1:2] are used by the UART, so this keeps SPI on a free connector.
##
## Standard single-bit SPI:
## pmod_spi_csn JC1
## pmod_spi_dq[0] JC2 MOSI
## pmod_spi_dq[1] JC3 MISO
## pmod_spi_sck JC4
## Optional quad lines, enabled by software mode:
## pmod_spi_dq[2] JC7
## pmod_spi_dq[3] JC8
set_property PACKAGE_PIN AC26 [get_ports pmod_spi_csn]
set_property PACKAGE_PIN AJ27 [get_ports {pmod_spi_dq[0]}]
set_property PACKAGE_PIN AH30 [get_ports {pmod_spi_dq[1]}]
set_property PACKAGE_PIN AK29 [get_ports pmod_spi_sck]
set_property PACKAGE_PIN AD26 [get_ports {pmod_spi_dq[2]}]
set_property PACKAGE_PIN AG30 [get_ports {pmod_spi_dq[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {pmod_spi_sck pmod_spi_csn pmod_spi_dq[*]}]
set_property DRIVE 8 [get_ports {pmod_spi_sck pmod_spi_csn pmod_spi_dq[*]}]
set_property SLEW SLOW [get_ports {pmod_spi_sck pmod_spi_csn pmod_spi_dq[*]}]