14 lines
670 B
Tcl
14 lines
670 B
Tcl
## VCU118 PMOD0/J52 GPS RF input.
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## The connector side is 3.3 V through U41; FPGA U1 side is LVCMOS18.
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## This 16.367981 MHz input is also the GPS acquisition/tracking PLL reference.
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set_property PACKAGE_PIN AY14 [get_ports rf_clk_pmod]
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set_property IOSTANDARD LVCMOS18 [get_ports rf_clk_pmod]
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create_clock -period 61.095 -name pmod_rf_clk [get_ports rf_clk_pmod]
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set_property PACKAGE_PIN AY15 [get_ports {rf_data_pmod[0]}]
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set_property PACKAGE_PIN AW15 [get_ports {rf_data_pmod[1]}]
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set_property PACKAGE_PIN AV15 [get_ports {rf_data_pmod[2]}]
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set_property PACKAGE_PIN AV16 [get_ports {rf_data_pmod[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {rf_data_pmod[*]}]
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