33 lines
1.5 KiB
Tcl
33 lines
1.5 KiB
Tcl
## VCU118 Evaluation Platform, xcvu9p-flga2104-2L-e.
|
|
## Pins are taken from the Vivado 2025.2 VCU118 2.4 board file.
|
|
|
|
set_property PACKAGE_PIN G31 [get_ports sysclk1_300_p]
|
|
set_property PACKAGE_PIN F31 [get_ports sysclk1_300_n]
|
|
set_property IOSTANDARD DIFF_SSTL12 [get_ports {sysclk1_300_p sysclk1_300_n}]
|
|
create_clock -period 3.333 -name sysclk1_300 [get_ports sysclk1_300_p]
|
|
|
|
# Async clock groups and optional RF/Ethernet pins are mode-dependent.
|
|
# build.tcl reads the matching companion XDC and applies clock groups after synth.
|
|
|
|
set_property PACKAGE_PIN L19 [get_ports cpu_reset]
|
|
set_property IOSTANDARD LVCMOS12 [get_ports cpu_reset]
|
|
|
|
set_property PACKAGE_PIN BB21 [get_ports rs232_uart_txd]
|
|
set_property PACKAGE_PIN AW25 [get_ports rs232_uart_rxd]
|
|
set_property IOSTANDARD LVCMOS18 [get_ports {rs232_uart_txd rs232_uart_rxd}]
|
|
set_property DRIVE 8 [get_ports rs232_uart_txd]
|
|
|
|
set_property PACKAGE_PIN AT32 [get_ports {led[0]}]
|
|
set_property PACKAGE_PIN AV34 [get_ports {led[1]}]
|
|
set_property PACKAGE_PIN AY30 [get_ports {led[2]}]
|
|
set_property PACKAGE_PIN BB32 [get_ports {led[3]}]
|
|
set_property PACKAGE_PIN BF32 [get_ports {led[4]}]
|
|
set_property PACKAGE_PIN AU37 [get_ports {led[5]}]
|
|
set_property PACKAGE_PIN AV36 [get_ports {led[6]}]
|
|
set_property PACKAGE_PIN BA37 [get_ports {led[7]}]
|
|
set_property IOSTANDARD LVCMOS12 [get_ports led[*]]
|
|
set_property DRIVE 8 [get_ports led[*]]
|
|
|
|
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
|
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|