Files
gps/hardware/fpga/vcu118/rtl/Makefile
T
2026-07-12 11:01:51 +03:00

19 lines
502 B
Makefile

.PHONY: help all shell generated clean
help:
@echo "VCU118 RTL targets:"
@echo " make shell # list hand-written FPGA shell RTL"
@echo " make generated # generate Rocket SystemVerilog and wrapper"
@echo " make clean # remove generated wrapper/verilog"
all: generated
shell:
@find . -type f -name '*.sv' -print | sort
generated:
@make -C ../../../../targets/fpga/vcu118 rtl
clean:
rm -rf ../../../generated/vcu118-soc-verilog ../../../../targets/fpga/vcu118/out/build/generated