138 lines
8.1 KiB
Plaintext
138 lines
8.1 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2025.2 (64-bit)
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# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
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# IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
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# SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
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# Start of session at: Sat Jul 11 11:04:38 2026
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# Process ID : 4308
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# Current directory : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs
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# Command line : vivado -mode batch -log /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log -journal /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou -source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
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# Log file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.log
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# Journal file : /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/logs/write_flash.jou
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# Running On : onur
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# Platform : Ubuntu
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# Operating System : Ubuntu 22.04.5 LTS
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# Processor Detail : AMD Ryzen 7 7800X3D 8-Core Processor
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# CPU Frequency : 4199.924 MHz
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# CPU Physical cores : 12
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# CPU Logical cores : 12
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# Host memory : 22112 MB
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# Swap memory : 2147 MB
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# Total Virtual : 24260 MB
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# Available Virtual : 21217 MB
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#-----------------------------------------------------------
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Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
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Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
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source /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/write_flash.tcl
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# set script_dir [file dirname [file normalize [info script]]]
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# set fpga_dir [file normalize [file join $script_dir ../..]]
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# proc getenv_default {name default} {
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# if {[info exists ::env($name)] && $::env($name) ne ""} {
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# return $::env($name)
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# }
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# return $default
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# }
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# proc region_end {offset file} {
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# return [expr {$offset + [file size $file]}]
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# }
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# set bit_file [file normalize [getenv_default BIT_FILE [file join $fpga_dir out bitstream genesys2_rocket.bit]]]
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# set app_image [file normalize [getenv_default APP_FLASH_IMAGE [file join $fpga_dir out flash hello_uart.flash.bin]]]
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# set mcs_file [file normalize [getenv_default FLASH_MCS [file join $fpga_dir out flash genesys2_rocket.mcs]]]
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# set bin_file [file normalize [getenv_default FLASH_BIN [file join $fpga_dir out flash genesys2_rocket.bin]]]
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# set flash_size_mb [getenv_default FLASH_SIZE_MB 32]
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# set flash_interface [getenv_default FLASH_INTERFACE SPIx4]
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# set bitstream_offset [getenv_default BITSTREAM_OFFSET 0x00000000]
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# set app_flash_offset [getenv_default APP_FLASH_OFFSET 0x01800000]
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# file mkdir [file dirname $mcs_file]
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# file mkdir [file dirname $bin_file]
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# if {![file exists $bit_file]} {
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# error "Bitstream not found: $bit_file"
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# }
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# if {![file exists $app_image]} {
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# error "Application flash image not found: $app_image"
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# }
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# set flash_size_bytes [expr {$flash_size_mb * 1024 * 1024}]
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# set bitstream_end [region_end $bitstream_offset $bit_file]
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# set app_end [region_end $app_flash_offset $app_image]
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# if {$bitstream_end > $flash_size_bytes} {
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# error [format "Bitstream region exceeds flash: end=0x%08x flash_size=0x%08x" $bitstream_end $flash_size_bytes]
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# }
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# if {$app_end > $flash_size_bytes} {
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# error [format "App region exceeds flash: end=0x%08x flash_size=0x%08x" $app_end $flash_size_bytes]
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# }
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# if {$bitstream_offset < $app_end && $app_flash_offset < $bitstream_end} {
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# error [format "Bitstream/app flash regions overlap: bit=[0x%08x,0x%08x) app=[0x%08x,0x%08x)" \
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# $bitstream_offset $bitstream_end $app_flash_offset $app_end]
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# }
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# puts "Generating flash MCS:"
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Generating flash MCS:
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# puts " bitstream: $bit_file @ $bitstream_offset"
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bitstream: /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit @ 0x00000000
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# puts " app image: $app_image @ $app_flash_offset"
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app image: /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin @ 0x01800000
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# puts " size/interface: ${flash_size_mb}MiB $flash_interface"
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size/interface: 32MiB SPIx4
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# puts [format " flash size: 0x%08x bytes" $flash_size_bytes]
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flash size: 0x02000000 bytes
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# puts [format " bitstream end: 0x%08x" $bitstream_end]
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bitstream end: 0x00ae9e20
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# puts [format " app end: 0x%08x" $app_end]
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app end: 0x018134a0
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# write_cfgmem -force -format MCS -size $flash_size_mb -interface $flash_interface \
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# -loadbit "up $bitstream_offset $bit_file" \
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# -loaddata "up $app_flash_offset $app_image" \
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# $mcs_file
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Command: write_cfgmem -force -format MCS -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
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Creating config memory files...
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Creating bitstream load up from address 0x00000000
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Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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Creating bitstream load up from address 0x01800000
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Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
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Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
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Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
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===================================
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Configuration Memory information
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===================================
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File Format MCS
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Interface SPIX4
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Size 32M
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Start Address 0x00000000
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End Address 0x01FFFFFF
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Addr1 Addr2 Date File(s)
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0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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0x01800000 0x0181349F Jul 11 11:04:37 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
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0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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write_cfgmem completed successfully
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# write_cfgmem -force -format BIN -size $flash_size_mb -interface $flash_interface \
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# -loadbit "up $bitstream_offset $bit_file" \
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# -loaddata "up $app_flash_offset $app_image" \
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# $bin_file
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Command: write_cfgmem -force -format BIN -size 32 -interface SPIx4 -loadbit {up 0x00000000 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit} -loaddata {up 0x01800000 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin} /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
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Creating config memory files...
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Creating bitstream load up from address 0x00000000
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Loading bitfile /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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Creating bitstream load up from address 0x01800000
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Loading datafile /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
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Writing file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
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Writing log file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.prm
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===================================
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Configuration Memory information
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===================================
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File Format BIN
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Interface SPIX4
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Size 32M
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Start Address 0x00000000
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End Address 0x01FFFFFF
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Addr1 Addr2 Date File(s)
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0x00000000 0x00AE9D9B Jul 10 16:50:38 2026 /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
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0x01800000 0x0181349F Jul 11 11:04:37 2026 /home/onur/Desktop/rocket/rocket-chip/soc/out/flash/gps_system.flash.bin
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0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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write_cfgmem completed successfully
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# puts "Wrote $mcs_file"
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Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.mcs
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# puts "Wrote $bin_file"
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Wrote /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/flash/genesys2_rocket.bin
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INFO: [Common 17-206] Exiting Vivado at Sat Jul 11 11:04:44 2026...
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