7930 lines
924 KiB
Plaintext
7930 lines
924 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
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| Date : Sat Jul 11 20:02:33 2026
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| Host : onur running 64-bit Ubuntu 22.04.5 LTS
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| Command : report_drc -file /home/onur/Desktop/rocket/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt
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| Design : genesys2_rocket_top
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| Device : xc7k325tffg900-2
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| Speed File : -2
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| Design State : Fully Routed
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Report DRC
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Table of Contents
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-----------------
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1. REPORT SUMMARY
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2. REPORT DETAILS
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1. REPORT SUMMARY
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-----------------
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Netlist: genesys2_rocket_top
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Floorplan: design_1
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Design limits: <entire design considered>
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Ruledeck: default
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Max checks: <unlimited>
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Checks found: 1577
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+-----------+----------+-----------------------------+--------+
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| Rule | Severity | Description | Checks |
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+-----------+----------+-----------------------------+--------+
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| CHECK-3 | Warning | Report rule limit reached | 2 |
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| DPIP-1 | Warning | Input pipelining | 305 |
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| DPOP-1 | Warning | PREG Output pipelining | 106 |
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| DPOP-2 | Warning | MREG Output pipelining | 184 |
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| DPOR-1 | Warning | Asynchronous load check | 927 |
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| DPREG-4 | Warning | DSP48E1_PregDynOpmodeZmuxP: | 4 |
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| PDRC-153 | Warning | Gated clock check | 9 |
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| REQP-1839 | Warning | RAMB36 async control check | 20 |
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| REQP-1840 | Warning | RAMB18 async control check | 20 |
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+-----------+----------+-----------------------------+--------+
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2. REPORT DETAILS
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-----------------
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CHECK-3#1 Warning
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Report rule limit reached
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REQP-1839 rule limit reached: 20 violations have been found.
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Related violations: <none>
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CHECK-3#2 Warning
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Report rule limit reached
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REQP-1840 rule limit reached: 20 violations have been found.
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Related violations: <none>
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DPIP-1#1 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#2 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#3 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#4 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#5 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#6 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#7 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#8 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#9 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#10 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#11 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#12 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#13 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#14 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#15 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#16 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#17 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#18 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#19 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#20 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#21 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#22 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#23 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#24 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#25 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#26 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#27 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#28 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#29 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#30 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#31 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#32 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#33 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#34 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#35 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#36 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#37 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#38 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#39 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#40 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#41 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#42 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
|
|
|
|
DPIP-1#43 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#44 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#45 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#46 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#47 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#48 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#49 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#50 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#51 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#52 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#53 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#54 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#55 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#56 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#57 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#58 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#59 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#60 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#61 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#62 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#63 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#64 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#65 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#66 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#67 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#68 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#69 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#70 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#71 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#72 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#73 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#74 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#75 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#76 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#77 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 input u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/C[47:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#78 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#79 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#80 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#81 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#82 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#83 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#84 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#85 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#86 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#87 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#88 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#89 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#90 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
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Related violations: <none>
|
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|
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DPIP-1#91 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
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Related violations: <none>
|
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|
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DPIP-1#92 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
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DPIP-1#93 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
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DPIP-1#94 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
|
DPIP-1#95 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
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DPIP-1#96 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__5/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
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DPIP-1#97 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
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DPIP-1#98 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__6/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#99 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#100 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
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DPIP-1#101 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#102 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__8/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#103 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#104 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__9/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#105 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#106 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#107 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#108 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#109 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#110 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#111 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#112 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#113 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#114 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#115 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#116 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#117 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#118 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#119 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__5/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#120 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__5/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#121 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__6/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#122 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__6/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#123 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__7 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__7/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#124 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__7 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__7/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#125 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__8 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__8/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#126 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__8 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__8/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#127 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__9 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__9/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#128 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__9 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__9/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#129 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#130 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#131 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#132 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__0 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#133 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#134 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__1 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__1/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#135 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#136 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#137 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__3/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#138 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__3 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__3/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#139 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#140 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#141 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__5/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#142 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__5 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__5/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#143 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__6/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#144 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__6 input u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__6/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#145 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#146 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#147 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#148 Warning
|
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Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#149 Warning
|
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Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#150 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#151 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#152 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#153 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#154 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#155 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#156 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#157 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#158 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#159 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
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DPIP-1#160 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
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DPIP-1#161 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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DPIP-1#162 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
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DPIP-1#163 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
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DPIP-1#164 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
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DPIP-1#165 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
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DPIP-1#166 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#167 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#168 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#169 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#170 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#171 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#172 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#173 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#174 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#175 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#176 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#177 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#178 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#179 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#180 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#181 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#182 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#183 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#184 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#185 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#186 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#187 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#188 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#189 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#190 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#191 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#192 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#193 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#194 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#195 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#196 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#197 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#198 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#199 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#200 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#201 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#202 Warning
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Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#203 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#204 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#205 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#206 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#207 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#208 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
|
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|
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DPIP-1#209 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#210 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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|
Related violations: <none>
|
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|
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DPIP-1#211 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
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|
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DPIP-1#212 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
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|
|
DPIP-1#213 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
|
DPIP-1#214 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#215 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
|
DPIP-1#216 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#217 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#218 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#219 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#220 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#221 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#222 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#223 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#224 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#225 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#226 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#227 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#228 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#229 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#230 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#231 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#232 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#233 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#234 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#235 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#236 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#237 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#238 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#239 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#240 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#241 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#242 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#243 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#244 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#245 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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DPIP-1#246 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#247 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#248 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#249 Warning
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Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#250 Warning
|
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Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#251 Warning
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Input pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#252 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#253 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#254 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#255 Warning
|
|
Input pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#256 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#257 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#258 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#259 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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|
Related violations: <none>
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DPIP-1#260 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#261 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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DPIP-1#262 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
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DPIP-1#263 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
|
DPIP-1#264 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#265 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#266 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
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|
|
DPIP-1#267 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#268 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#269 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#270 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#271 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#272 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#273 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#274 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#275 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#276 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#277 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#278 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#279 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#280 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#281 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_carr_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_carr_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#282 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult10 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult10/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#283 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult20 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult20/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#284 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#285 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#286 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#287 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#288 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#289 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#290 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#291 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#292 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#293 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#294 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
|
|
Related violations: <none>
|
|
|
|
DPIP-1#295 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#296 Warning
|
|
Input pipelining
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|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#297 Warning
|
|
Input pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 input u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#298 Warning
|
|
Input pipelining
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|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#299 Warning
|
|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#300 Warning
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|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__1 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#301 Warning
|
|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__2/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#302 Warning
|
|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#303 Warning
|
|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#304 Warning
|
|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/A[29:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPIP-1#305 Warning
|
|
Input pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 input u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/B[17:0] is not pipelined. Pipelining DSP48 input will improve performance.
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Related violations: <none>
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DPOP-1#1 Warning
|
|
PREG Output pipelining
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|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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DPOP-1#2 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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|
DPOP-1#3 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#4 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
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|
DPOP-1#5 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#6 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#7 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#8 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#9 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#10 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#11 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#12 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#13 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#14 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#15 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#16 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#17 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#18 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#19 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#20 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#21 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#22 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#23 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#24 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#25 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#26 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#27 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#28 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#29 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#30 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#31 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#32 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 output u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#33 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#34 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#35 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#36 Warning
|
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#37 Warning
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PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#38 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#39 Warning
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|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
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Related violations: <none>
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DPOP-1#40 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
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Related violations: <none>
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DPOP-1#41 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
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Related violations: <none>
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|
DPOP-1#42 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#43 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#44 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#45 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#46 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#47 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#48 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#49 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#50 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
DPOP-1#51 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#52 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
DPOP-1#53 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
DPOP-1#54 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#55 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#56 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#57 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#58 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#59 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#60 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#61 Warning
|
|
PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#62 Warning
|
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#63 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#64 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#65 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#66 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#67 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#68 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#69 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#70 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#71 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#72 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#73 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#74 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#75 Warning
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PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
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Related violations: <none>
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DPOP-1#76 Warning
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|
PREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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|
DPOP-1#77 Warning
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|
PREG Output pipelining
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|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
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Related violations: <none>
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|
DPOP-1#78 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#79 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
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|
DPOP-1#80 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
DPOP-1#81 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
DPOP-1#82 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
DPOP-1#83 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#84 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#85 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#86 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#87 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#88 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
DPOP-1#89 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1 output u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#90 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#91 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#92 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#93 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#94 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__0 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
|
|
|
|
DPOP-1#95 Warning
|
|
PREG Output pipelining
|
|
DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__2 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
|
|
Related violations: <none>
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|
|
|
DPOP-1#96 Warning
|
|
PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__4 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#97 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__5 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#98 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__7 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#99 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__8 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__8/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#100 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#101 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__1 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#102 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#103 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__5 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__5/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#104 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__7 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__7/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#105 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-1#106 Warning
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PREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 output u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function. If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function. If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
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Related violations: <none>
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DPOP-2#1 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ac/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#2 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/ad/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#3 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bc/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#4 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/comp_mult_inst/bd/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#5 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/k0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#6 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#7 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#8 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#9 Warning
|
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MREG Output pipelining
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|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#10 Warning
|
|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/port1_addr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#11 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#12 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_imag_w1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
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Related violations: <none>
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DPOP-2#13 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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|
Related violations: <none>
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DPOP-2#14 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/butterfly_i/x1_real_w1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#15 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/k0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#16 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_code_inst/port1_addr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#17 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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|
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DPOP-2#18 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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|
DPOP-2#19 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#20 Warning
|
|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#21 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#22 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#23 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#24 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#25 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#26 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_imag_w1__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#27 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#28 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#29 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#30 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#31 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#32 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/butterfly_i/x1_real_w1__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#33 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/k0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#34 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0 multiplier stage u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_inst/port1_addr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#35 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#36 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#37 Warning
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|
MREG Output pipelining
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|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#38 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__2 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#39 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#40 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#41 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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|
Related violations: <none>
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DPOP-2#42 Warning
|
|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#43 Warning
|
|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#44 Warning
|
|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#45 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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|
Related violations: <none>
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DPOP-2#46 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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|
Related violations: <none>
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DPOP-2#47 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__4 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
|
Related violations: <none>
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DPOP-2#48 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__7 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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|
Related violations: <none>
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DPOP-2#49 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#50 Warning
|
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__0 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#51 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#52 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__3 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__3/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#53 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#54 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__6 multiplier stage u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__6/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#55 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#56 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#57 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#58 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#59 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#60 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#61 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#62 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#63 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#64 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#65 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#66 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#67 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#68 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#69 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#70 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#71 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#72 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#73 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#74 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#75 Warning
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|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#76 Warning
|
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#77 Warning
|
|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#78 Warning
|
|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#79 Warning
|
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MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#80 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#81 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#82 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#83 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#84 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#85 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#86 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#87 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#88 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#89 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#90 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#91 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#92 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#93 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#94 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#95 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#96 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#97 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#98 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#99 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#100 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#101 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#102 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#103 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#104 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#105 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
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Related violations: <none>
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DPOP-2#106 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
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Related violations: <none>
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DPOP-2#107 Warning
|
|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
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Related violations: <none>
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DPOP-2#108 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
|
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Related violations: <none>
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DPOP-2#109 Warning
|
|
MREG Output pipelining
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#110 Warning
|
|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#111 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#112 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#113 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#114 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#115 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#116 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#117 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#118 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#119 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#120 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#121 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#122 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#123 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#124 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#125 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#126 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#127 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#128 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#129 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#130 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#131 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#132 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#133 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#134 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#135 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#136 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#137 Warning
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|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#138 Warning
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|
MREG Output pipelining
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#139 Warning
|
|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#140 Warning
|
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#141 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#142 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#143 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#144 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#145 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#146 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#147 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#148 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#149 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#150 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#151 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#152 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#153 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#154 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#155 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#156 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#157 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#158 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#159 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_carr_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_carr_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#160 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult10 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult10/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#161 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult20 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/LF_code_i/mult20/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#162 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#163 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#164 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#165 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__2 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#166 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#167 Warning
|
|
MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#168 Warning
|
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#169 Warning
|
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#170 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#171 Warning
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MREG Output pipelining
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0__0 multiplier stage u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#172 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__0 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#173 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__2 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#174 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__4 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#175 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__5 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#176 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__7 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#177 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__8 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/core/div/remainder1__8/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#178 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#179 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__1 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#180 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__4/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#181 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__5 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__5/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#182 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__7 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/dfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__7/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#183 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOP-2#184 Warning
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MREG Output pipelining
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DSP u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0 multiplier stage u_rocket/tile_prci_domain/element_reset_domain/rockettile/fpuOpt/sfma/fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function. If this multiplier was inferred, it is suggested to describe an additional register stage after this function. If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used. If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
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Related violations: <none>
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DPOR-1#1 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#2 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#3 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#4 Warning
|
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#5 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#6 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#7 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#8 Warning
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#9 Warning
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#10 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#11 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#12 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#13 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#14 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#15 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#16 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#17 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/im_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#18 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#19 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#20 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#21 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#22 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#23 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#24 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#25 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#26 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#27 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#28 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#29 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#30 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#31 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#32 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#33 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#34 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/ifft_abs_sqr_inst/re_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#35 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#36 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#37 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#38 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#39 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#40 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#41 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#42 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#43 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#44 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#45 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#46 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#47 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#48 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#49 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#50 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#51 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#52 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[0]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#53 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[10]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#54 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[11]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#55 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[12]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#56 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[13]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#57 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[14]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#58 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[15]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#59 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#60 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[1]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#61 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[2]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#62 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[3]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#63 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[4]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#64 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[5]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#65 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[6]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#66 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[7]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#67 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[8]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#68 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/fraction_ticks_work_reg[9]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#69 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#70 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#71 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#72 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#73 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#74 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#75 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#76 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#77 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#78 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#79 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#80 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#81 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#82 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#83 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#84 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#85 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/ki_product_work_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#86 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#87 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#88 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#89 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#90 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#91 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#92 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#93 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#94 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#95 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#96 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#97 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#98 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#99 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#100 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#101 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#102 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work0__0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/kp_product_work_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#103 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
|
DPOR-1#104 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
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DPOR-1#105 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#106 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
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DPOR-1#107 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
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DPOR-1#108 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
|
|
|
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DPOR-1#109 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
|
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DPOR-1#110 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#111 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
|
|
|
|
DPOR-1#112 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#113 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#114 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#115 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#116 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#117 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#118 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#119 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#120 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[0]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#121 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[10]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#122 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[11]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#123 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[12]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#124 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[13]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#125 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[14]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#126 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[15]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#127 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#128 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[1]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#129 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[2]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#130 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[3]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#131 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[4]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#132 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[5]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#133 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[6]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#134 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[7]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#135 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[8]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#136 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__2 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[9]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#137 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[0]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#138 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[10]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#139 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[11]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#140 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[12]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#141 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[13]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#142 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[14]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#143 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[15]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#144 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[16]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#145 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[1]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#146 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[2]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#147 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[3]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#148 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[4]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#149 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[5]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#150 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[6]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#151 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[7]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#152 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[8]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#153 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work0__4 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/pps/i_pps_core/reference_age_work_reg[9]__3). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#154 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#155 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#156 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#157 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#158 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#159 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#160 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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DPOR-1#161 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#162 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#163 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#164 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
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|
|
DPOR-1#165 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#166 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#167 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#168 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#169 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#170 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#171 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#172 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#173 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#174 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#175 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#176 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#177 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#178 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#179 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#180 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#181 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#182 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#183 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#184 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#185 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#186 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#187 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#188 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#189 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#190 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#191 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#192 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#193 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#194 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#195 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#196 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#197 Warning
|
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#198 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#199 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#200 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#201 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#202 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#203 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#204 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#205 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#206 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#207 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#208 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#209 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#210 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#211 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#212 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#213 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#214 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#215 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#216 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#217 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#218 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#219 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#220 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#221 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#222 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#223 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#224 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#225 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#226 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#227 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#228 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#229 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#230 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#231 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#232 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#233 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#234 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#235 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#236 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#237 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#238 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#239 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#240 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#241 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#242 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#243 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#244 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#245 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#246 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#247 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#248 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#249 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#250 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#251 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#252 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#253 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#254 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#255 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#256 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#257 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#258 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#259 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#260 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#261 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#262 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#263 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#264 Warning
|
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#265 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#266 Warning
|
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#267 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#268 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#269 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#270 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#271 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#272 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#273 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#274 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
DPOR-1#275 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#276 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#277 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#278 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#279 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#280 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#281 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#282 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#283 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#284 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#285 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#286 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#287 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#288 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#289 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#290 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#291 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#292 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#293 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#294 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#295 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#296 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#297 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#298 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#299 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#300 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#301 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#302 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#303 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#304 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#305 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#306 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#307 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#308 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#309 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#310 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#311 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#312 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#313 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#314 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#315 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#316 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#317 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#318 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#319 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#320 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#321 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#322 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#323 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#324 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#325 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#326 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#327 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#328 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#329 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#330 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#331 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#332 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#333 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#334 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
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DPOR-1#335 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#336 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#337 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#338 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#339 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#340 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#341 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#342 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#343 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#344 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#345 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#346 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#347 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#348 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#349 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#350 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#351 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
|
DPOR-1#352 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
|
|
DPOR-1#353 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
DPOR-1#354 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
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|
|
DPOR-1#355 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#356 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#357 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#358 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#359 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#360 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#361 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#362 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#363 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#364 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#365 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#366 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#367 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#368 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#369 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#370 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#371 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#372 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#373 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#374 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#375 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#376 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#377 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#378 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#379 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#380 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#381 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#382 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#383 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#384 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#385 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#386 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#387 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
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DPOR-1#388 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
DPOR-1#389 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
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|
|
DPOR-1#390 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#391 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#392 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#393 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#394 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#395 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#396 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#397 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#398 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#399 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#400 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#401 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#402 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#403 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#404 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#405 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#406 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#407 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#408 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#409 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#410 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#411 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#412 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#413 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#414 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#415 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#416 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#417 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#418 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#419 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#420 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#421 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#422 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#423 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#424 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
|
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|
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DPOR-1#425 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#426 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#427 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#428 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#429 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#430 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#431 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#432 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#433 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#434 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#435 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#436 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#437 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#438 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#439 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#440 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#441 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#442 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#443 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#444 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#445 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#446 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#447 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#448 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#449 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#450 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#451 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#452 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#453 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#454 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#455 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#456 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#457 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#458 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#459 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#460 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#461 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#462 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#463 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#464 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#465 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#466 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#467 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#468 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#469 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#470 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#471 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#472 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#473 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#474 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#475 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#476 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#477 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#478 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#479 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#480 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#481 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#482 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#483 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#484 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#485 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
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DPOR-1#486 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#487 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#488 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#489 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#490 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#491 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#492 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#493 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#494 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#495 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#496 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#497 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#498 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#499 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#500 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#501 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#502 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#503 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#504 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
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DPOR-1#505 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#506 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#507 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#508 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#509 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#510 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#511 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#512 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#513 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#514 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#515 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#516 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#517 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#518 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#519 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#520 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#521 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#522 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#523 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#524 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#525 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#526 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#527 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#528 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#529 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#530 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#531 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#532 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#533 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#534 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#535 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#536 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#537 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#538 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#539 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#540 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#541 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#542 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#543 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#544 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#545 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#546 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#547 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#548 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#549 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#550 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#551 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#552 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#553 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#554 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#555 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#556 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#557 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#558 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#559 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#560 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#561 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#562 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#563 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#564 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#565 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#566 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#567 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#568 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#569 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#570 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#571 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#572 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#573 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#574 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#575 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
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DPOR-1#576 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#577 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#578 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#579 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#580 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#581 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#582 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#583 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#584 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#585 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#586 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#587 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#588 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#589 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#590 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#591 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#592 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#593 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#594 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#595 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#596 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#597 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#598 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#599 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#600 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#601 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#602 Warning
|
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#603 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#604 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#605 Warning
|
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Asynchronous load check
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|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#606 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#607 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#608 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#609 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#610 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#611 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#612 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#613 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#614 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#615 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#616 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#617 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#618 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#619 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#620 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#621 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#622 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#623 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#624 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#625 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#626 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#627 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#628 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#629 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#630 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#631 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#632 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#633 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#634 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#635 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#636 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#637 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#638 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#639 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#640 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#641 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#642 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#643 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#644 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#645 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#646 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#647 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#648 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#649 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#650 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#651 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#652 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#653 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#654 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#655 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#656 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#657 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#658 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#659 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#660 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#661 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#662 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#663 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#664 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#665 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#666 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#667 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#668 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#669 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#670 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#671 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#672 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#673 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#674 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#675 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#676 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#677 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#678 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#679 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#680 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#681 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#682 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#683 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#684 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#685 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#686 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#687 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#688 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#689 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#690 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#691 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#692 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#693 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#694 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#695 Warning
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Asynchronous load check
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#696 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#697 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#698 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#699 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#700 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#701 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#702 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#703 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#704 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#705 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#706 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
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|
|
DPOR-1#707 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#708 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#709 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#710 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#711 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#712 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#713 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#714 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#715 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#716 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#717 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#718 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#719 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#720 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#721 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#722 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#723 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#724 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#725 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#726 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#727 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#728 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#729 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#730 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#731 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#732 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#733 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#734 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#735 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#736 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#737 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#738 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#739 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#740 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#741 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#742 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#743 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#744 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#745 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#746 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#747 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#748 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#749 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#750 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#751 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
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DPOR-1#752 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
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DPOR-1#753 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#754 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
DPOR-1#755 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
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DPOR-1#756 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
|
DPOR-1#757 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
|
|
DPOR-1#758 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
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DPOR-1#759 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
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|
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DPOR-1#760 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#761 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#762 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#763 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#764 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#765 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#766 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#767 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#768 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#769 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#770 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#771 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#772 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#773 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#774 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#775 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#776 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#777 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#778 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#779 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#780 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#781 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#782 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#783 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#784 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#785 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#786 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#787 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#788 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#789 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#790 Warning
|
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#791 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#792 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#793 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#794 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#795 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#796 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#797 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#798 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
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DPOR-1#799 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
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DPOR-1#800 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#801 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
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Related violations: <none>
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|
|
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DPOR-1#802 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#803 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#804 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#805 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#806 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#807 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#808 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#809 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#810 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#811 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#812 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#813 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#814 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#815 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#816 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#817 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#818 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#819 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#820 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#821 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#822 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#823 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#824 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#825 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#826 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
|
DPOR-1#827 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#828 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#829 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
|
|
|
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DPOR-1#830 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#831 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPOR-1#832 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#833 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#834 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#835 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#836 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#837 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#838 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#839 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#840 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#841 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#842 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#843 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#844 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#845 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#846 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#847 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#848 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#849 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#850 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#851 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#852 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#853 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#854 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#855 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#856 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#857 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#858 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#859 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word0__1 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/NCO_carr_i/freq_word_reg[16]__1). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#860 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#861 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#862 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#863 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#864 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#865 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPOR-1#866 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#867 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#868 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
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DPOR-1#869 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
|
|
DPOR-1#870 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#871 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#872 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#873 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
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DPOR-1#874 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#875 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
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DPOR-1#876 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/i_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#877 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#878 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#879 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#880 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#881 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#882 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#883 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#884 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#885 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#886 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#887 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#888 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#889 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#890 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#891 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#892 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#893 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/cos2x_i/q_p_sqr_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#894 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#895 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#896 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#897 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#898 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#899 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#900 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#901 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#902 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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|
|
|
DPOR-1#903 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#904 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#905 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#906 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#907 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#908 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#909 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#910 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/i_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#911 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[0]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#912 Warning
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|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[10]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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DPOR-1#913 Warning
|
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[11]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#914 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[12]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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Related violations: <none>
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DPOR-1#915 Warning
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Asynchronous load check
|
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DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[13]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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|
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DPOR-1#916 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[14]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
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|
Related violations: <none>
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DPOR-1#917 Warning
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Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[15]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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DPOR-1#918 Warning
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|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[16]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#919 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[1]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
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DPOR-1#920 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[2]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
|
DPOR-1#921 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[3]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#922 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[4]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#923 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[5]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
DPOR-1#924 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[6]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
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|
|
DPOR-1#925 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[7]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#926 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[8]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPOR-1#927 Warning
|
|
Asynchronous load check
|
|
DSP u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r0 output is connected to registers with an asynchronous reset (u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/lock_detector_i/q_prompt_energy_r_reg[9]). This is preventing the possibility of merging these registers in to the DSP Block since the DSP block registers only possess synchronous reset capability. It is suggested to recode or change these registers to remove the reset or use a synchronous reset to get the best optimization for performance, power and area.
|
|
Related violations: <none>
|
|
|
|
DPREG-4#1 Warning
|
|
DSP48E1_PregDynOpmodeZmuxP:
|
|
The DSP48E1 cell u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out with the given dynamic OPMODE[6:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0
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Related violations: <none>
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|
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DPREG-4#2 Warning
|
|
DSP48E1_PregDynOpmodeZmuxP:
|
|
The DSP48E1 cell u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__0 with the given dynamic OPMODE[6:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0
|
|
Related violations: <none>
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|
|
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DPREG-4#3 Warning
|
|
DSP48E1_PregDynOpmodeZmuxP:
|
|
The DSP48E1 cell u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__1 with the given dynamic OPMODE[6:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0
|
|
Related violations: <none>
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|
|
|
DPREG-4#4 Warning
|
|
DSP48E1_PregDynOpmodeZmuxP:
|
|
The DSP48E1 cell u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/fft_IQ_inst/p_1_out__2 with the given dynamic OPMODE[6:0] connections may lead to an unregistered asynchronous feedback path without the PREG attribute enabled. Please refer to the user guide and if one of the internal P feedback opmodes is possible for this design the PREG attribute must be set to 1, currently set to 0
|
|
Related violations: <none>
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|
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PDRC-153#1 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_0/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_0/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_0/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
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|
Related violations: <none>
|
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|
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PDRC-153#2 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_1/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_1/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_1/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#3 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_2/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_2/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_2/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#4 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_3/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_3/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_3/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#5 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_4/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_4/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_4/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#6 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_5/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_5/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_5/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#7 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_6/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_6/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_6/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#8 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_7/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_7/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_7/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
PDRC-153#9 Warning
|
|
Gated clock check
|
|
Net u_rocket/fpga_gps_domain/dev/tracking_8/i___5_n_0 is a gated clock net sourced by a combinational pin u_rocket/fpga_gps_domain/dev/tracking_8/i___5/O, cell u_rocket/fpga_gps_domain/dev/tracking_8/i___5. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#1 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
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REQP-1839#2 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
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REQP-1839#3 Warning
|
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RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
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REQP-1839#4 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
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|
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REQP-1839#5 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
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REQP-1839#6 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
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|
|
REQP-1839#7 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
|
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|
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REQP-1839#8 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
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|
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REQP-1839#9 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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|
Related violations: <none>
|
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|
|
REQP-1839#10 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#11 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#12 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#13 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#14 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#15 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#16 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#17 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#18 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#19 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1839#20 Warning
|
|
RAMB36 async control check
|
|
The RAMB36E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_0/ADDRBWRADDR[14] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1840#1 Warning
|
|
RAMB18 async control check
|
|
The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[12] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1840#2 Warning
|
|
RAMB18 async control check
|
|
The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[12] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
|
|
Related violations: <none>
|
|
|
|
REQP-1840#3 Warning
|
|
RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[12] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#4 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[12] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#5 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[12] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#6 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[12] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[12]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#7 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#8 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[10]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#9 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[11]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#10 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#11 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[13]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#12 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#13 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#14 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#15 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[4]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#16 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[5]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#17 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[6]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#18 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[7]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#19 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[8]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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REQP-1840#20 Warning
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RAMB18 async control check
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The RAMB18E1 u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25 has an input control pin u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/ram_reg_25/ADDRBWRADDR[13] (net: u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/bram_i/rd_addr[13]) which is driven by a register (u_rocket/fpga_gps_domain/dev/acq/i_acq_top/acq_corr_inst/acq_peak_srch_inst/rd_offset_reg[9]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
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Related violations: <none>
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