141 lines
11 KiB
C++
141 lines
11 KiB
C++
//===- FIRRTLAnnotationDetails.h.inc - Annotation Details ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Auto-generated annotation class name constants.
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//
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// THIS FILE IS AUTOMATICALLY GENERATED. DO NOT EDIT!
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// Generated from FIRRTLAnnotations.td using circt-tblgen.
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//
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//===----------------------------------------------------------------------===//
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/// Adds a prefix to the module name during compilation.
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constexpr const char *modulePrefixAnnoClass = "chisel3.ModulePrefixAnnotation";
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/// Marks a signal for tracing with its Chisel type information.
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constexpr const char *traceAnnoClass = "chisel3.experimental.Trace$TraceAnnotation";
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/// Specifies a trace name for the annotated signal.
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constexpr const char *traceNameAnnoClass = "chisel3.experimental.Trace$TraceNameAnnotation";
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/// Forces a specific name for the annotated component, preventing name changes
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constexpr const char *forceNameAnnoClass = "chisel3.util.experimental.ForceNameAnnotation";
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/// Annotation for decode table specifications in Chisel.
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constexpr const char *decodeTableAnnoClass = "chisel3.util.experimental.decode.DecodeTableAnnotation";
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/// Specify the type lowering option for module internal signals. This is similar
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constexpr const char *bodyTypeLoweringAnnoClass = "circt.BodyTypeLoweringAnnotation";
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/// Specify the port convention for a module. The port convention controls how a
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constexpr const char *conventionAnnoClass = "circt.ConventionAnnotation";
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/// This annotation indicates that the target module should be excluded from the
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constexpr const char *excludeFromFullResetAnnoClass = "circt.ExcludeFromFullResetAnnotation";
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/// The target must be a signal that is a reset. The type of the signal must be
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constexpr const char *fullResetAnnoClass = "circt.FullResetAnnotation";
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/// Specify the output directory for a module. The target must be a public
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constexpr const char *outputDirAnnoClass = "circt.OutputDirAnnotation";
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/// Specifies verbatim black box source code with one or more files. Each file
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constexpr const char *verbatimBlackBoxAnnoClass = "circt.VerbatimBlackBoxAnno";
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/// Attaches SV attributes to a specified target. A reference target must be a
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constexpr const char *attributeAnnoClass = "firrtl.AttributeAnnotation";
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/// Attaches a comment to a specified target. A reference target must be a wire,
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constexpr const char *docStringAnnoClass = "firrtl.DocStringAnnotation";
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/// Specifies a file to load memory contents from during simulation.
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constexpr const char *loadMemoryAnnoClass = "firrtl.annotations.LoadMemoryAnnotation";
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/// Specifies inline memory file loading for simulation.
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constexpr const char *memoryFileInlineAnnoClass = "firrtl.annotations.MemoryFileInlineAnnotation";
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/// This is used to represent an index in to an aggregate type, such as an index
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constexpr const char *fieldAnnoClass = "firrtl.annotations.TargetToken$Field";
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/// Indicates that the target should be inlined.
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constexpr const char *inlineAnnoClass = "firrtl.passes.InlineAnnotation";
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/// Marks a component as a wiring sink for the WiringTransform.
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constexpr const char *sinkAnnoClass = "firrtl.passes.wiring.SinkAnnotation";
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/// Marks a component as a wiring source for the WiringTransform.
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constexpr const char *sourceAnnoClass = "firrtl.passes.wiring.SourceAnnotation";
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/// Specifies a FIRRTL transform to run during compilation. This annotation
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constexpr const char *runFirrtlTransformAnnoClass = "firrtl.stage.RunFirrtlTransformAnnotation";
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/// Attached to any external module created from any of the other blackbox
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constexpr const char *blackBoxAnnoClass = "firrtl.transforms.BlackBox";
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/// Specifies the black box source code (`text`) inline. Generates a file with
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constexpr const char *blackBoxInlineAnnoClass = "firrtl.transforms.BlackBoxInlineAnno";
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/// Specifies the file `path` as source code for the module. Copies the file to
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constexpr const char *blackBoxPathAnnoClass = "firrtl.transforms.BlackBoxPathAnno";
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/// Overrides the target directory into which black box source files are emitted.
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constexpr const char *blackBoxTargetDirAnnoClass = "firrtl.transforms.BlackBoxTargetDirAnno";
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/// This annotation assigns the targeted module to a dedup group. Modules that
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constexpr const char *dedupGroupAnnoClass = "firrtl.transforms.DedupGroupAnnotation";
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/// Prevents the removal of elements through optimization.
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constexpr const char *dontTouchAnnoClass = "firrtl.transforms.DontTouchAnnotation";
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/// Indicates that the target should be flattened, which means that child
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constexpr const char *flattenAnnoClass = "firrtl.transforms.FlattenAnnotation";
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/// This annotation causes the deduplication pass to check that the listed
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constexpr const char *mustDeduplicateAnnoClass = "firrtl.transforms.MustDeduplicateAnnotation";
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/// Prevents deduplication of the annotated module. Both regular modules and
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constexpr const char *noDedupAnnoClass = "firrtl.transforms.NoDedupAnnotation";
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/// Marks an external module as an internal verification black box for RocketChip.
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constexpr const char *internalVerifBlackBoxAnnoClass = "freechips.rocketchip.annotations.InternalVerifBlackBoxAnnotation";
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/// This annotation is used to mark modules which should be retimed, and is
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constexpr const char *retimeModuleAnnoClass = "freechips.rocketchip.util.RetimeModuleAnnotation";
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/// This annotation causes an extra port to be added to all SRAM modules in the
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constexpr const char *addSeqMemPortAnnoClass = "sifive.enterprise.firrtl.AddSeqMemPortAnnotation";
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/// This annotation is used to emit metadata about the extra ports created by
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constexpr const char *addSeqMemPortsFileAnnoClass = "sifive.enterprise.firrtl.AddSeqMemPortsFileAnnotation";
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/// Circuit-level annotation that converts all memories in the design to register vectors.
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constexpr const char *convertMemToRegOfVecAnnoClass = "sifive.enterprise.firrtl.ConvertMemToRegOfVecAnnotation$";
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/// Triggers extraction of assertions to a separate file.
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constexpr const char *extractAssertionsAnnoClass = "sifive.enterprise.firrtl.ExtractAssertionsAnnotation";
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/// Triggers extraction of assumptions to a separate file.
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constexpr const char *extractAssumptionsAnnoClass = "sifive.enterprise.firrtl.ExtractAssumptionsAnnotation";
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/// This annotation causes the `ExtractInstances` pass to move the annotated
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constexpr const char *extractBlackBoxAnnoClass = "sifive.enterprise.firrtl.ExtractBlackBoxAnnotation";
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/// This annotation causes the `ExtractInstances` pass to move instances of
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constexpr const char *extractClockGatesFileAnnoClass = "sifive.enterprise.firrtl.ExtractClockGatesFileAnnotation";
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/// Triggers extraction of coverage statements to a separate file.
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constexpr const char *extractCoverageAnnoClass = "sifive.enterprise.firrtl.ExtractCoverageAnnotation";
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/// This annotation causes the `ExtractInstances` pass to move memory instances
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constexpr const char *extractSeqMemsFileAnnoClass = "sifive.enterprise.firrtl.ExtractSeqMemsFileAnnotation";
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/// The target must be a signal that is or is inferred to be an asynchronous reset.
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constexpr const char *fullAsyncResetAnnoClass = "sifive.enterprise.firrtl.FullAsyncResetAnnotation";
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/// This annotation indicates that the target should be excluded from the
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constexpr const char *ignoreFullAsyncResetAnnoClass = "sifive.enterprise.firrtl.IgnoreFullAsyncResetAnnotation";
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/// This annotation can be used to add an extra level of hierarchy in the design
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constexpr const char *injectDUTHierarchyAnnoClass = "sifive.enterprise.firrtl.InjectDUTHierarchyAnnotation";
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/// This annotation is used to mark the top module of the device under test. This
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constexpr const char *markDUTAnnoClass = "sifive.enterprise.firrtl.MarkDUTAnnotation";
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/// This annotation is used to define the directory where metadata should be
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constexpr const char *metadataDirAnnoClass = "sifive.enterprise.firrtl.MetadataDirAnnotation";
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/// This annotation indicates that a module hierarchy JSON file should be emitted
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constexpr const char *moduleHierarchyAnnoClass = "sifive.enterprise.firrtl.ModuleHierarchyAnnotation";
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/// This annotation triggers the creation of a file containing a JSON array
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constexpr const char *retimeModulesAnnoClass = "sifive.enterprise.firrtl.RetimeModulesAnnotation";
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/// This annotation triggers the creation of a file containing a JSON array of
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constexpr const char *sitestBlackBoxAnnoClass = "sifive.enterprise.firrtl.SitestBlackBoxAnnotation";
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/// This annotation is used to specify additional library names that should be
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constexpr const char *sitestBlackBoxLibrariesAnnoClass = "sifive.enterprise.firrtl.SitestBlackBoxLibrariesAnnotation";
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/// This annotation triggers the creation of a file containing a JSON array of
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constexpr const char *sitestTestHarnessBlackBoxAnnoClass = "sifive.enterprise.firrtl.SitestTestHarnessBlackBoxAnnotation";
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/// This annotation is used to indicate where to emit the test bench modules
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constexpr const char *testBenchDirAnnoClass = "sifive.enterprise.firrtl.TestBenchDirAnnotation";
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/// This annotation indicates that a module hierarchy JSON file should be emitted
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constexpr const char *testHarnessHierarchyAnnoClass = "sifive.enterprise.firrtl.TestHarnessHierarchyAnnotation";
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/// Specifies the path to the test harness module.
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constexpr const char *testHarnessPathAnnoClass = "sifive.enterprise.firrtl.TestHarnessPathAnnotation";
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/// Creates a SystemVerilog interface for each bundle type in Grand Central views.
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constexpr const char *augmentedBundleTypeAnnoClass = "sifive.enterprise.grandcentral.AugmentedBundleType";
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/// Creates a SystemVerilog logic type for Grand Central views.
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constexpr const char *augmentedGroundTypeAnnoClass = "sifive.enterprise.grandcentral.AugmentedGroundType";
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/// Creates a SystemVerilog unpacked array for Grand Central views.
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constexpr const char *augmentedVectorTypeAnnoClass = "sifive.enterprise.grandcentral.AugmentedVectorType";
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/// This annotation controls where to "extract" Grand Central collateral from
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constexpr const char *extractGrandCentralAnnoClass = "sifive.enterprise.grandcentral.ExtractGrandCentralAnnotation";
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/// This annotation, if present, will emit a YAML representation of all
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constexpr const char *grandCentralHierarchyFileAnnoClass = "sifive.enterprise.grandcentral.GrandCentralHierarchyFileAnnotation";
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/// These annotations are used to represent a SystemVerilog interface, a location
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constexpr const char *serializedViewAnnoClass = "sifive.enterprise.grandcentral.GrandCentralView$SerializedViewAnnotation";
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/// Annotation for memory taps in Grand Central. This annotation has custom
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constexpr const char *memTapAnnoClass = "sifive.enterprise.grandcentral.MemTapAnnotation";
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/// Annotation for Grand Central views. Similar to SerializedViewAnnotation but
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constexpr const char *viewAnnoClass = "sifive.enterprise.grandcentral.ViewAnnotation";
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/// Companion annotation for Grand Central views. Not in SFC (Scala FIRRTL Compiler).
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constexpr const char *companionAnnoClass = "sifive.enterprise.grandcentral.ViewAnnotation.companion";
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