478 lines
20 KiB
C++
478 lines
20 KiB
C++
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Rewriters *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* From: LTL.td *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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static ::llvm::LogicalResult static_dag_matcher_0(::mlir::PatternRewriter &rewriter, ::mlir::Operation *op0, ::llvm::SmallVector<::mlir::Operation *, 4> &tblgen_ops, ::mlir::Operation::operand_range &inputs) {
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(void)tblgen_ops;
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auto castedOp1 = ::llvm::dyn_cast<circt::ltl::ConcatOp>(op0); (void)castedOp1;
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if (!(castedOp1)){
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return rewriter.notifyMatchFailure(op0, [&](::mlir::Diagnostic &diag) {
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diag << "castedOp1 is not circt::ltl::ConcatOp type";
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});
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}
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inputs = castedOp1.getODSOperands(0);
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return ::mlir::success();
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}
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/* Generated from:
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LTLFolds.td:86
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*/
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struct FlattenConcats : public ::mlir::RewritePattern {
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FlattenConcats(::mlir::MLIRContext *context)
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: ::mlir::RewritePattern("ltl.concat", 1, context, {"ltl.concat"}) {}
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::llvm::LogicalResult matchAndRewrite(::mlir::Operation *op0,
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::mlir::PatternRewriter &rewriter) const override {
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// Variables for capturing values and attributes used while creating ops
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::mlir::Operation::operand_range inputs(op0->getOperands());
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::llvm::SmallVector<::mlir::Operation *, 4> tblgen_ops;
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// Match
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tblgen_ops.push_back(op0);
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if(::mlir::failed(static_dag_matcher_0(rewriter, op0, tblgen_ops, inputs))) {
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return ::mlir::failure();
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}
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auto castedOp0 = ::llvm::dyn_cast_or_null<circt::ltl::ConcatOp>(op0); (void)castedOp0;
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if (!((
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llvm::any_of(inputs, [](auto v){
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return !!v.template getDefiningOp<ConcatOp>();
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})
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))){
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return rewriter.notifyMatchFailure(op0, [&](::mlir::Diagnostic &diag) {
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diag << "entities 'inputs' failed to satisfy constraint: 'any value is defined by ConcatOp'";
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});
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}
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// Rewrite
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auto odsLoc = rewriter.getFusedLoc({tblgen_ops[0]->getLoc()}); (void)odsLoc;
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::llvm::SmallVector<::mlir::Value, 4> tblgen_repl_values;
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auto nativeVar_0 = flattenConcats(inputs); (void)nativeVar_0;
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circt::ltl::ConcatOp tblgen_ConcatOp_1;
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{
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::llvm::SmallVector<::mlir::Value, 4> tblgen_values; (void)tblgen_values;
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circt::ltl::ConcatOp::Properties tblgen_props; (void)tblgen_props;
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for (auto v: nativeVar_0) {
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tblgen_values.push_back(v);
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}
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::llvm::SmallVector<::mlir::Type, 4> tblgen_types; (void)tblgen_types;
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for (auto v: castedOp0.getODSResults(0)) {
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tblgen_types.push_back(v.getType());
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}
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tblgen_ConcatOp_1 = circt::ltl::ConcatOp::create(rewriter, odsLoc, tblgen_types, tblgen_values, tblgen_props);
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}
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for (auto v: ::llvm::SmallVector<::mlir::Value, 4>{ tblgen_ConcatOp_1.getODSResults(0) }) {
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tblgen_repl_values.push_back(v);
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}
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rewriter.replaceOp(op0, tblgen_repl_values);
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return ::mlir::success();
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}
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};
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/* Generated from:
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LTLFolds.td:68
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*/
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struct MoveClockedDelayIntoConcat : public ::mlir::RewritePattern {
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MoveClockedDelayIntoConcat(::mlir::MLIRContext *context)
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: ::mlir::RewritePattern("ltl.clocked_delay", 2, context, {"ltl.clocked_delay", "ltl.concat"}) {}
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::llvm::LogicalResult matchAndRewrite(::mlir::Operation *op0,
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::mlir::PatternRewriter &rewriter) const override {
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// Variables for capturing values and attributes used while creating ops
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::mlir::IntegerAttr length;
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::mlir::IntegerAttr delay;
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::mlir::Operation::operand_range clock(op0->getOperands());
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circt::ltl::ClockEdgeAttr edge;
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::mlir::Operation::operand_range inputs(op0->getOperands());
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::llvm::SmallVector<::mlir::Operation *, 4> tblgen_ops;
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// Match
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tblgen_ops.push_back(op0);
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auto castedOp0 = ::llvm::dyn_cast<circt::ltl::ClockedDelayOp>(op0); (void)castedOp0;
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{
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auto *op1 = (*castedOp0.getODSOperands(0).begin()).getDefiningOp();
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if (!(op1)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "There's no operation that defines operand 0 of castedOp0";
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});
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}
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if(::mlir::failed(static_dag_matcher_0(rewriter, op1, tblgen_ops, inputs))) {
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return ::mlir::failure();
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}
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tblgen_ops.push_back(op1);
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getEdge();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.clocked_delay' to have attribute 'edge' of type 'circt::ltl::ClockEdgeAttr'";
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});
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}
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edge = tblgen_attr;
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}
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clock = castedOp0.getODSOperands(1);
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getDelay();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.clocked_delay' to have attribute 'delay' of type '::mlir::IntegerAttr'";
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});
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}
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delay = tblgen_attr;
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getLength();
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length = tblgen_attr;
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}
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// Rewrite
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auto odsLoc = rewriter.getFusedLoc({tblgen_ops[0]->getLoc(), tblgen_ops[1]->getLoc()}); (void)odsLoc;
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::llvm::SmallVector<::mlir::Value, 4> tblgen_repl_values;
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auto nativeVar_0 = inputs[0]; (void)nativeVar_0;
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circt::ltl::ClockedDelayOp tblgen_ClockedDelayOp_1;
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{
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::mlir::Value tblgen_value_0 = nativeVar_0;
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::mlir::Value tblgen_value_1 = (*clock.begin());
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tblgen_ClockedDelayOp_1 = circt::ltl::ClockedDelayOp::create(rewriter, odsLoc,
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/*input=*/tblgen_value_0,
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/*edge=*/edge,
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/*clock=*/tblgen_value_1,
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/*delay=*/delay,
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/*length=*/length
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);
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}
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auto nativeVar_2 = inputs.drop_front(); (void)nativeVar_2;
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auto nativeVar_3 = concatValues(ValueRange{tblgen_ClockedDelayOp_1}, ValueRange{nativeVar_2}); (void)nativeVar_3;
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circt::ltl::ConcatOp tblgen_ConcatOp_4;
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{
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::llvm::SmallVector<::mlir::Value, 4> tblgen_values; (void)tblgen_values;
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circt::ltl::ConcatOp::Properties tblgen_props; (void)tblgen_props;
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for (auto v: nativeVar_3) {
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tblgen_values.push_back(v);
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}
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::llvm::SmallVector<::mlir::Type, 4> tblgen_types; (void)tblgen_types;
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for (auto v: castedOp0.getODSResults(0)) {
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tblgen_types.push_back(v.getType());
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}
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tblgen_ConcatOp_4 = circt::ltl::ConcatOp::create(rewriter, odsLoc, tblgen_types, tblgen_values, tblgen_props);
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}
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for (auto v: ::llvm::SmallVector<::mlir::Value, 4>{ tblgen_ConcatOp_4.getODSResults(0) }) {
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tblgen_repl_values.push_back(v);
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}
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rewriter.replaceOp(op0, tblgen_repl_values);
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return ::mlir::success();
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}
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};
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/* Generated from:
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LTLFolds.td:48
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*/
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struct MoveDelayIntoConcat : public ::mlir::RewritePattern {
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MoveDelayIntoConcat(::mlir::MLIRContext *context)
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: ::mlir::RewritePattern("ltl.delay", 2, context, {"ltl.concat", "ltl.delay"}) {}
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::llvm::LogicalResult matchAndRewrite(::mlir::Operation *op0,
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::mlir::PatternRewriter &rewriter) const override {
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// Variables for capturing values and attributes used while creating ops
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::mlir::IntegerAttr length;
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::mlir::IntegerAttr delay;
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::mlir::Operation::operand_range inputs(op0->getOperands());
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::llvm::SmallVector<::mlir::Operation *, 4> tblgen_ops;
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// Match
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tblgen_ops.push_back(op0);
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auto castedOp0 = ::llvm::dyn_cast<circt::ltl::DelayOp>(op0); (void)castedOp0;
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{
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auto *op1 = (*castedOp0.getODSOperands(0).begin()).getDefiningOp();
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if (!(op1)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "There's no operation that defines operand 0 of castedOp0";
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});
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}
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if(::mlir::failed(static_dag_matcher_0(rewriter, op1, tblgen_ops, inputs))) {
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return ::mlir::failure();
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}
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tblgen_ops.push_back(op1);
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getDelay();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.delay' to have attribute 'delay' of type '::mlir::IntegerAttr'";
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});
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}
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delay = tblgen_attr;
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getLength();
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length = tblgen_attr;
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}
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// Rewrite
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auto odsLoc = rewriter.getFusedLoc({tblgen_ops[0]->getLoc(), tblgen_ops[1]->getLoc()}); (void)odsLoc;
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::llvm::SmallVector<::mlir::Value, 4> tblgen_repl_values;
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auto nativeVar_0 = inputs[0]; (void)nativeVar_0;
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circt::ltl::DelayOp tblgen_DelayOp_1;
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{
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::mlir::Value tblgen_value_0 = nativeVar_0;
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tblgen_DelayOp_1 = circt::ltl::DelayOp::create(rewriter, odsLoc,
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/*input=*/tblgen_value_0,
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/*delay=*/delay,
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/*length=*/length
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);
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}
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auto nativeVar_2 = inputs.drop_front(); (void)nativeVar_2;
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auto nativeVar_3 = concatValues(ValueRange{tblgen_DelayOp_1}, ValueRange{nativeVar_2}); (void)nativeVar_3;
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circt::ltl::ConcatOp tblgen_ConcatOp_4;
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{
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::llvm::SmallVector<::mlir::Value, 4> tblgen_values; (void)tblgen_values;
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circt::ltl::ConcatOp::Properties tblgen_props; (void)tblgen_props;
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for (auto v: nativeVar_3) {
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tblgen_values.push_back(v);
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}
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::llvm::SmallVector<::mlir::Type, 4> tblgen_types; (void)tblgen_types;
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for (auto v: castedOp0.getODSResults(0)) {
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tblgen_types.push_back(v.getType());
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}
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tblgen_ConcatOp_4 = circt::ltl::ConcatOp::create(rewriter, odsLoc, tblgen_types, tblgen_values, tblgen_props);
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}
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for (auto v: ::llvm::SmallVector<::mlir::Value, 4>{ tblgen_ConcatOp_4.getODSResults(0) }) {
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tblgen_repl_values.push_back(v);
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}
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rewriter.replaceOp(op0, tblgen_repl_values);
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return ::mlir::success();
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}
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};
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/* Generated from:
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LTLFolds.td:59
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*/
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struct NestedClockedDelays : public ::mlir::RewritePattern {
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NestedClockedDelays(::mlir::MLIRContext *context)
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: ::mlir::RewritePattern("ltl.clocked_delay", 2, context, {"ltl.clocked_delay"}) {}
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::llvm::LogicalResult matchAndRewrite(::mlir::Operation *op0,
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::mlir::PatternRewriter &rewriter) const override {
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// Variables for capturing values and attributes used while creating ops
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::mlir::IntegerAttr length1;
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::mlir::IntegerAttr delay1;
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::mlir::Operation::operand_range clock1(op0->getOperands());
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::mlir::IntegerAttr delay0;
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circt::ltl::ClockEdgeAttr edge1;
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::mlir::Operation::operand_range clock0(op0->getOperands());
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::mlir::IntegerAttr length0;
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circt::ltl::ClockEdgeAttr edge0;
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::mlir::Operation::operand_range input(op0->getOperands());
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::llvm::SmallVector<::mlir::Operation *, 4> tblgen_ops;
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// Match
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tblgen_ops.push_back(op0);
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auto castedOp0 = ::llvm::dyn_cast<circt::ltl::ClockedDelayOp>(op0); (void)castedOp0;
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{
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auto *op1 = (*castedOp0.getODSOperands(0).begin()).getDefiningOp();
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if (!(op1)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "There's no operation that defines operand 0 of castedOp0";
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});
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}
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auto castedOp1 = ::llvm::dyn_cast<circt::ltl::ClockedDelayOp>(op1); (void)castedOp1;
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if (!(castedOp1)){
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return rewriter.notifyMatchFailure(op1, [&](::mlir::Diagnostic &diag) {
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diag << "castedOp1 is not circt::ltl::ClockedDelayOp type";
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});
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}
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input = castedOp1.getODSOperands(0);
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{
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[[maybe_unused]] auto tblgen_attr = castedOp1.getProperties().getEdge();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp1, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.clocked_delay' to have attribute 'edge' of type 'circt::ltl::ClockEdgeAttr'";
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});
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}
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edge0 = tblgen_attr;
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}
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clock0 = castedOp1.getODSOperands(1);
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{
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[[maybe_unused]] auto tblgen_attr = castedOp1.getProperties().getDelay();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp1, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.clocked_delay' to have attribute 'delay' of type '::mlir::IntegerAttr'";
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});
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}
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delay0 = tblgen_attr;
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp1.getProperties().getLength();
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length0 = tblgen_attr;
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}
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tblgen_ops.push_back(op1);
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getEdge();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.clocked_delay' to have attribute 'edge' of type 'circt::ltl::ClockEdgeAttr'";
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});
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}
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edge1 = tblgen_attr;
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}
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clock1 = castedOp0.getODSOperands(1);
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getDelay();
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if (!(tblgen_attr)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "expected op 'ltl.clocked_delay' to have attribute 'delay' of type '::mlir::IntegerAttr'";
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});
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}
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delay1 = tblgen_attr;
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}
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{
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[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getLength();
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length1 = tblgen_attr;
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}
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if (!(((*clock0.begin()) == (*clock1.begin()) && edge0 == edge1))){
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return rewriter.notifyMatchFailure(op0, [&](::mlir::Diagnostic &diag) {
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diag << "entities 'clock0, clock1, edge0, edge1' failed to satisfy constraint: ''";
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});
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}
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// Rewrite
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auto odsLoc = rewriter.getFusedLoc({tblgen_ops[0]->getLoc(), tblgen_ops[1]->getLoc()}); (void)odsLoc;
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::llvm::SmallVector<::mlir::Value, 4> tblgen_repl_values;
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auto nativeVar_0 = rewriter.getI64IntegerAttr(delay0.getInt() + delay1.getInt()); (void)nativeVar_0;
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auto nativeVar_1 =
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length0 && length1 ? rewriter.getI64IntegerAttr(length0.getInt() + length1.getInt())
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: IntegerAttr{}
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; (void)nativeVar_1;
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circt::ltl::ClockedDelayOp tblgen_ClockedDelayOp_2;
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{
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::llvm::SmallVector<::mlir::Value, 4> tblgen_values; (void)tblgen_values;
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circt::ltl::ClockedDelayOp::Properties tblgen_props; (void)tblgen_props;
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tblgen_values.push_back((*input.begin()));
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tblgen_props.edge = ::llvm::dyn_cast_if_present<decltype(tblgen_props.edge)>(edge0);
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tblgen_values.push_back((*clock0.begin()));
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tblgen_props.delay = ::llvm::dyn_cast_if_present<decltype(tblgen_props.delay)>(nativeVar_0);
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tblgen_props.length = ::llvm::dyn_cast_if_present<decltype(tblgen_props.length)>(nativeVar_1);
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::llvm::SmallVector<::mlir::Type, 4> tblgen_types; (void)tblgen_types;
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for (auto v: castedOp0.getODSResults(0)) {
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tblgen_types.push_back(v.getType());
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}
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tblgen_ClockedDelayOp_2 = circt::ltl::ClockedDelayOp::create(rewriter, odsLoc, tblgen_types, tblgen_values, tblgen_props);
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}
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for (auto v: ::llvm::SmallVector<::mlir::Value, 4>{ tblgen_ClockedDelayOp_2.getODSResults(0) }) {
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tblgen_repl_values.push_back(v);
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}
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rewriter.replaceOp(op0, tblgen_repl_values);
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return ::mlir::success();
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}
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};
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/* Generated from:
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LTLFolds.td:42
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*/
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struct NestedDelays : public ::mlir::RewritePattern {
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NestedDelays(::mlir::MLIRContext *context)
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: ::mlir::RewritePattern("ltl.delay", 2, context, {"ltl.delay"}) {}
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::llvm::LogicalResult matchAndRewrite(::mlir::Operation *op0,
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::mlir::PatternRewriter &rewriter) const override {
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// Variables for capturing values and attributes used while creating ops
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::mlir::IntegerAttr delay2;
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::mlir::IntegerAttr length1;
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::mlir::IntegerAttr delay1;
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::mlir::IntegerAttr length2;
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::mlir::Operation::operand_range input(op0->getOperands());
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::llvm::SmallVector<::mlir::Operation *, 4> tblgen_ops;
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// Match
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tblgen_ops.push_back(op0);
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auto castedOp0 = ::llvm::dyn_cast<circt::ltl::DelayOp>(op0); (void)castedOp0;
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{
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auto *op1 = (*castedOp0.getODSOperands(0).begin()).getDefiningOp();
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if (!(op1)){
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return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
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diag << "There's no operation that defines operand 0 of castedOp0";
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});
|
|
}
|
|
auto castedOp1 = ::llvm::dyn_cast<circt::ltl::DelayOp>(op1); (void)castedOp1;
|
|
if (!(castedOp1)){
|
|
return rewriter.notifyMatchFailure(op1, [&](::mlir::Diagnostic &diag) {
|
|
diag << "castedOp1 is not circt::ltl::DelayOp type";
|
|
});
|
|
}
|
|
input = castedOp1.getODSOperands(0);
|
|
{
|
|
[[maybe_unused]] auto tblgen_attr = castedOp1.getProperties().getDelay();
|
|
if (!(tblgen_attr)){
|
|
return rewriter.notifyMatchFailure(castedOp1, [&](::mlir::Diagnostic &diag) {
|
|
diag << "expected op 'ltl.delay' to have attribute 'delay' of type '::mlir::IntegerAttr'";
|
|
});
|
|
}
|
|
delay1 = tblgen_attr;
|
|
}
|
|
{
|
|
[[maybe_unused]] auto tblgen_attr = castedOp1.getProperties().getLength();
|
|
length1 = tblgen_attr;
|
|
}
|
|
tblgen_ops.push_back(op1);
|
|
}
|
|
{
|
|
[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getDelay();
|
|
if (!(tblgen_attr)){
|
|
return rewriter.notifyMatchFailure(castedOp0, [&](::mlir::Diagnostic &diag) {
|
|
diag << "expected op 'ltl.delay' to have attribute 'delay' of type '::mlir::IntegerAttr'";
|
|
});
|
|
}
|
|
delay2 = tblgen_attr;
|
|
}
|
|
{
|
|
[[maybe_unused]] auto tblgen_attr = castedOp0.getProperties().getLength();
|
|
length2 = tblgen_attr;
|
|
}
|
|
|
|
// Rewrite
|
|
auto odsLoc = rewriter.getFusedLoc({tblgen_ops[0]->getLoc(), tblgen_ops[1]->getLoc()}); (void)odsLoc;
|
|
::llvm::SmallVector<::mlir::Value, 4> tblgen_repl_values;
|
|
auto nativeVar_0 = rewriter.getI64IntegerAttr(delay1.getInt() + delay2.getInt()); (void)nativeVar_0;
|
|
auto nativeVar_1 =
|
|
length1 && length2 ? rewriter.getI64IntegerAttr(length1.getInt() + length2.getInt())
|
|
: IntegerAttr{}
|
|
; (void)nativeVar_1;
|
|
circt::ltl::DelayOp tblgen_DelayOp_2;
|
|
{
|
|
::llvm::SmallVector<::mlir::Value, 4> tblgen_values; (void)tblgen_values;
|
|
circt::ltl::DelayOp::Properties tblgen_props; (void)tblgen_props;
|
|
tblgen_values.push_back((*input.begin()));
|
|
tblgen_props.delay = ::llvm::dyn_cast_if_present<decltype(tblgen_props.delay)>(nativeVar_0);
|
|
tblgen_props.length = ::llvm::dyn_cast_if_present<decltype(tblgen_props.length)>(nativeVar_1);
|
|
::llvm::SmallVector<::mlir::Type, 4> tblgen_types; (void)tblgen_types;
|
|
for (auto v: castedOp0.getODSResults(0)) {
|
|
tblgen_types.push_back(v.getType());
|
|
}
|
|
tblgen_DelayOp_2 = circt::ltl::DelayOp::create(rewriter, odsLoc, tblgen_types, tblgen_values, tblgen_props);
|
|
}
|
|
|
|
for (auto v: ::llvm::SmallVector<::mlir::Value, 4>{ tblgen_DelayOp_2.getODSResults(0) }) {
|
|
tblgen_repl_values.push_back(v);
|
|
}
|
|
|
|
rewriter.replaceOp(op0, tblgen_repl_values);
|
|
return ::mlir::success();
|
|
}
|
|
};
|
|
|
|
[[maybe_unused]] void populateWithGenerated(::mlir::RewritePatternSet &patterns) {
|
|
patterns.add<FlattenConcats>(patterns.getContext());
|
|
patterns.add<MoveClockedDelayIntoConcat>(patterns.getContext());
|
|
patterns.add<MoveDelayIntoConcat>(patterns.getContext());
|
|
patterns.add<NestedClockedDelays>(patterns.getContext());
|
|
patterns.add<NestedDelays>(patterns.getContext());
|
|
}
|