onur
a25a1a61d0
Add freestanding S25FL256S read/program/erase/verify support and seed a newly formatted ephemeris store with stale records. Age-gate navigation readiness, persist the continuous Toe week, and regenerate the Genesys2 MAX2771 integration and flash image.
116 lines
4.9 KiB
Systemverilog
116 lines
4.9 KiB
Systemverilog
// Generated by CIRCT firtool-1.151.0
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module TLMAX2771SPI(
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input clock,
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reset,
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output auto_in_a_ready,
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input auto_in_a_valid,
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input [2:0] auto_in_a_bits_opcode,
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input [1:0] auto_in_a_bits_size,
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input [5:0] auto_in_a_bits_source,
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input [28:0] auto_in_a_bits_address,
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input [7:0] auto_in_a_bits_mask,
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input [63:0] auto_in_a_bits_data,
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input auto_in_d_ready,
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output auto_in_d_valid,
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output [2:0] auto_in_d_bits_opcode,
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output [1:0] auto_in_d_bits_size,
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output [5:0] auto_in_d_bits_source,
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output [63:0] auto_in_d_bits_data,
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output auto_sdata_oe_out,
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auto_sdata_out_out,
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input auto_sdata_in_in,
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output auto_csn_out,
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auto_sclk_out
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);
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wire _out_wofireMux_T_4;
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wire _out_T_26;
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wire _out_back_front_q_io_deq_valid;
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wire _out_back_front_q_io_deq_bits_read;
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wire [8:0] _out_back_front_q_io_deq_bits_index;
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wire [63:0] _out_back_front_q_io_deq_bits_data;
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wire [7:0] _out_back_front_q_io_deq_bits_mask;
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wire [31:0] _engine_read_data;
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wire _engine_busy;
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wire _engine_ready;
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reg [31:0] writeData;
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wire _out_out_bits_data_T_1 =
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_out_back_front_q_io_deq_bits_index[8:2] == 7'h0;
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wire out_womask =
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&{{8{_out_back_front_q_io_deq_bits_mask[3]}},
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{8{_out_back_front_q_io_deq_bits_mask[2]}},
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{8{_out_back_front_q_io_deq_bits_mask[1]}},
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{8{_out_back_front_q_io_deq_bits_mask[0]}}};
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wire _out_T_15 = _engine_ready | ~out_womask;
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wire out_womask_1 =
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&{{8{_out_back_front_q_io_deq_bits_mask[7]}},
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{8{_out_back_front_q_io_deq_bits_mask[6]}},
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{8{_out_back_front_q_io_deq_bits_mask[5]}},
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{8{_out_back_front_q_io_deq_bits_mask[4]}}};
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assign _out_T_26 = _engine_ready | ~out_womask_1;
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assign _out_wofireMux_T_4 =
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_out_back_front_q_io_deq_valid & auto_in_d_ready & ~_out_back_front_q_io_deq_bits_read
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& _out_back_front_q_io_deq_bits_index[1:0] == 2'h0 & _out_out_bits_data_T_1;
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wire [3:0] _GEN =
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{{1'h1},
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{1'h1},
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{1'h1},
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{|{_out_T_26 & _out_T_15, _out_back_front_q_io_deq_bits_index[8:2]}}};
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wire out_oready =
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_out_back_front_q_io_deq_bits_read | _GEN[_out_back_front_q_io_deq_bits_index[1:0]];
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wire [3:0][63:0] _GEN_0 =
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{{64'h4D41583100000007},
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{64'h367EE402FAF080},
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{{30'h0, _engine_busy, _engine_ready, _engine_read_data}},
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{64'h0}};
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always @(posedge clock) begin
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if (reset)
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writeData <= 32'h0;
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else if (_out_wofireMux_T_4 & _out_T_15 & out_womask_1 & _engine_ready)
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writeData <= _out_back_front_q_io_deq_bits_data[63:32];
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end // always @(posedge)
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max2771_spi_engine #(
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.CLOCK_HZ(50000000),
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.MAX_SCLK_HZ(4000000)
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) engine (
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.clk (clock),
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.rst_n (~reset),
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.start (_out_wofireMux_T_4 & _out_T_26 & out_womask & _engine_ready),
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.read_not_write (_out_back_front_q_io_deq_bits_data[8]),
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.address (_out_back_front_q_io_deq_bits_data[3:0]),
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.write_data (writeData),
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.read_data (_engine_read_data),
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.busy (_engine_busy),
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.ready (_engine_ready),
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.sclk (auto_sclk_out),
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.csn (auto_csn_out),
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.sdata_i (auto_sdata_in_in),
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.sdata_o (auto_sdata_out_out),
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.sdata_oe (auto_sdata_oe_out)
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);
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Queue1_RegMapperInput_i9_m8 out_back_front_q (
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.clock (clock),
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.reset (reset),
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.io_enq_ready (auto_in_a_ready),
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.io_enq_valid (auto_in_a_valid),
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.io_enq_bits_read (auto_in_a_bits_opcode == 3'h4),
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.io_enq_bits_index (auto_in_a_bits_address[11:3]),
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.io_enq_bits_data (auto_in_a_bits_data),
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.io_enq_bits_mask (auto_in_a_bits_mask),
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.io_enq_bits_extra_tlrr_extra_source (auto_in_a_bits_source),
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.io_enq_bits_extra_tlrr_extra_size (auto_in_a_bits_size),
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.io_deq_ready (auto_in_d_ready & out_oready),
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.io_deq_valid (_out_back_front_q_io_deq_valid),
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.io_deq_bits_read (_out_back_front_q_io_deq_bits_read),
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.io_deq_bits_index (_out_back_front_q_io_deq_bits_index),
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.io_deq_bits_data (_out_back_front_q_io_deq_bits_data),
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.io_deq_bits_mask (_out_back_front_q_io_deq_bits_mask),
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.io_deq_bits_extra_tlrr_extra_source (auto_in_d_bits_source),
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.io_deq_bits_extra_tlrr_extra_size (auto_in_d_bits_size)
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);
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assign auto_in_d_valid = _out_back_front_q_io_deq_valid & out_oready;
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assign auto_in_d_bits_opcode = {2'h0, _out_back_front_q_io_deq_bits_read};
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assign auto_in_d_bits_data =
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_out_out_bits_data_T_1 ? _GEN_0[_out_back_front_q_io_deq_bits_index[1:0]] : 64'h0;
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endmodule
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