a25a1a61d0
Add freestanding S25FL256S read/program/erase/verify support and seed a newly formatted ephemeris store with stale records. Age-gate navigation readiness, persist the continuous Toe week, and regenerate the Genesys2 MAX2771 integration and flash image.
490 lines
92 KiB
JSON
490 lines
92 KiB
JSON
[
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"/home/ankaoc/Desktop/gps_tdk_new/gps/hardware/generated/genesys2-soc"
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.RocketTile.traceCoreSourceNodeOut.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumDefAnnotation",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"definition":{
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"ITBrNTaken":4,
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"ITBrTaken":5,
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"ITReserved7":7,
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"ITExcReturn":3,
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"ITCoSwap":12,
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"ITInJump":15,
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"ITUnJump":14,
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"ITUnTail":10,
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"ITInterrupt":2,
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"ITException":1,
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"ITUnCall":8,
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"ITReserved6":6,
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"ITNothing":0,
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"ITReturn":13,
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"ITInTail":11,
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"ITInCall":9
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}
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.RocketTile.auto.trace_core_source_out.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.HierarchicalElementResetDomain.auto.rockettile_trace_core_source_out.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.TilePRCIDomain.auto.element_reset_domain_rockettile_trace_core_source_out.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_TraceCoreInterface.nodeIn.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_TraceCoreInterface.nodeOut.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_TraceCoreInterface.auto.out.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_TraceCoreInterface.auto.in.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"chisel3.experimental.EnumAnnotations$EnumVecAnnotation",
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"target":"VCU118RocketSystem.VCU118RocketSystem.traceCoreNodesIn.group",
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"typeName":"freechips.rocketchip.trace.TraceItype",
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"fields":[
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[
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"itype"
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]
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]
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockSinkDomain"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroupAggregator_aggregator"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroupAggregator_sbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroup"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_NoOutput"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLFIFOFixer"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLInterconnectCoupler_sbus_to_bus_named_cbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLInterconnectCoupler_sbus_from_bus_named_fbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLInterconnectCoupler_sbus_from_rockettile"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroupAggregator_pbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroup_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_NoOutput_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLFIFOFixer_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLXbar_pbus_in_i1_o1_a29d64s2k1z3u"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroupAggregator_fbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroup_2"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.FixedClockBroadcast_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_NoOutput_2"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLXbar_fbus_i1_o1_a32d64s1k1z4u"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.FrontBus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroupAggregator_cbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.ClockGroup_3"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_NoOutput_3"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLFIFOFixer_2"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLXbar_cbus_in_i1_o1_a32d64s2k1z4u"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLBuffer_a32d64s2k1z4u_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8_3"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLInterconnectCoupler_cbus_to_bus_named_pbus"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8_4"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLInterconnectCoupler_cbus_to_rockettile"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_UInt1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_UInt32"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_UInt1_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_TraceAux"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.BundleBridgeNexus_NoOutput_4"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8_5"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.store_data"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.data_raw"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.data_word_bypass"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.has_data"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.replay"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.mask"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.data"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.dv"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.dprv"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.signed"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.size"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.cmd"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.tag"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.bits.addr"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.resp.valid"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.s1_data.mask"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>io.cpu.s1_data.data"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.DTLB_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.Arbiter8_DCacheMetadataReq"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.Arbiter4_DCacheDataReq"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>s2_valid_cached_miss"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|DCache>s2_victim_dirty"
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},
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{
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"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
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"target":"~VCU118RocketSystem|DCache>data_plaOutput",
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"truthTable":"00->0\n01->1\n10->0\n ?",
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"minimizedTable":"01->1\n ?"
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},
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{
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"class":"firrtl.transforms.DontTouchAnnotation",
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"target":"~VCU118RocketSystem|ICache>s1_hit"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8_6"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLWidthWidget8_7"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLBuffer_a32d64s1k1z4u_1"
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},
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{
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"class":"firrtl.passes.InlineAnnotation",
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"target":"VCU118RocketSystem.TLBuffer_a32d64s2k1z3u"
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},
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{
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"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
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"target":"~VCU118RocketSystem|FPUDecoder>decoder_decoded",
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"truthTable":"?????00??????????????????1000011->0111100000000010010\n?????00??????????????????1000111->0111100000000010010\n?????00??????????????????1001011->0111100000000010010\n?????00??????????????????1001111->0111100000000010010\n0000000??????????????????1010011->0111001000000010010\n?????????????????010?????0000111->11000??????00000000\n?????????????????010?????0100111->100101?010001000000\n?????????????????011?????0000111->11000??????00000000\n?????????????????011?????0100111->100101?010101000000\n?????01??????????????????1000011->0111100010100010010\n?????01??????????????????1000111->0111100010100010010\n?????01??????????????????1001011->0111100010100010010\n?????01??????????????????1001111->0111100010100010010\n0000001??????????????????1010011->0111001010100010010\n0000100??????????????????1010011->0111001000000010010\n0000101??????????????????1010011->0111001010100010010\n0001000??????????????????1010011->0111000000000010010\n0001001??????????????????1010011->0111000010100010010\n0001100??????????????????1010011->0111000000000001010\n0001101??????????????????1010011->0111000010100001010\n0010000??????????000?????1010011->0111000000000100000\n0010000??????????001?????1010011->0111000000000100000\n0010000??????????010?????1010011->0111000000000100000\n0010001??????????000?????1010011->0111000010100100000\n0010001??????????001?????1010011->0111000010100100000\n0010001??????????010?????1010011->0111000010100100000\n0010100??????????000?????1010011->0111000000000100010\n0010100??????????001?????1010011->0111000000000100010\n0010101??????????000?????1010011->0111000010100100010\n0010101??????????001?????1010011->0111000010100100010\n010000000001?????????????1010011->011000?010000100010\n010000100000?????????????1010011->011000?000100100010\n010110000000?????????????1010011->011000?000000000110\n010110100000?????????????1010011->011000?010100000110\n1010000??????????000?????1010011->0011000000001000010\n1010000??????????001?????1010011->0011000000001000010\n1010000??????????010?????1010011->0011000000001000010\n1010001??????????000?????1010011->0011000010101000010\n1010001??????????001?????1010011->0011000010101000010\n1010001??????????010?????1010011->0011000010101000010\n110000000000?????????????1010011->001000?00??01000010\n110000000001?????????????1010011->001000?00??01000010\n110000000010?????????????1010011->001000?00??01000010\n110000000011?????????????1010011->001000?00??01000010\n110000100000?????????????1010011->001000?01??01000010\n110000100001?????????????1010011->001000?01??01000010\n110000100010?????????????1010011->001000?01??01000010\n110000100011?????????????1010011->001000?01??01000010\n110100000000?????????????1010011->01000??000010000010\n110100000001?????????????1010011->01000??000010000010\n110100000010?????????????1010011->01000??000010000010\n110100000011?????????????1010011->01000??000010000010\n110100100000?????????????1010011->01000??010110000010\n110100100001?????????????1010011->01000??010110000010\n110100100010?????????????1010011->01000??010110000010\n110100100011?????????????1010011->01000??010110000010\n111000000000?????000?????1010011->001000?010001000000\n111000000000?????001?????1010011->001000?000001000000\n111000100000?????000?????1010011->001000?010101000000\n111000100000?????001?????1010011->001000?010101000000\n111100000000?????000?????1010011->01000??000110000000\n111100100000?????000?????1010011->01000??010110000000\n ??????????????????0",
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{
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"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
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"target":"~VCU118RocketSystem|Rocket>id_ctrl_decoder_decoded",
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|
|
"minimizedTable":"000000000000????????????????????->1????????\n000000000001????????????????????->?1???????\n0001????????????????????????????->????1????\n0011000000??????????????????????->??1??????\n0011000001??????????????????????->???1?????\n01??????????????????????????????->??1??????\n ?????????"
|
|
},
|
|
{
|
|
"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
|
|
"target":"~VCU118RocketSystem|CSRFile>io_decode_0_fp_csr_plaOutput",
|
|
"truthTable":"000000000001->1\n000000000010->1\n000000000011->1\n001100000000->0\n001100000001->0\n001100000100->0\n001100000101->0\n001100100000->0\n001100100011->0\n001100100100->0\n001100100101->0\n001100100110->0\n001100100111->0\n001100101000->0\n001100101001->0\n001100101010->0\n001100101011->0\n001100101100->0\n001100101101->0\n001100101110->0\n001100101111->0\n001100110000->0\n001100110001->0\n001100110010->0\n001100110011->0\n001100110100->0\n001100110101->0\n001100110110->0\n001100110111->0\n001100111000->0\n001100111001->0\n001100111010->0\n001100111011->0\n001100111100->0\n001100111101->0\n001100111110->0\n001100111111->0\n001101000000->0\n001101000001->0\n001101000010->0\n001101000011->0\n001101000100->0\n001110100000->0\n001110100010->0\n001110110000->0\n001110110001->0\n001110110010->0\n001110110011->0\n001110110100->0\n001110110101->0\n001110110110->0\n001110110111->0\n001110111000->0\n001110111001->0\n001110111010->0\n001110111011->0\n001110111100->0\n001110111101->0\n001110111110->0\n001110111111->0\n011110100000->0\n011110100001->0\n011110100010->0\n011110100011->0\n011110110000->0\n011110110001->0\n011110110010->0\n011111000001->0\n101100000000->0\n101100000010->0\n101100000011->0\n101100000100->0\n101100000101->0\n101100000110->0\n101100000111->0\n101100001000->0\n101100001001->0\n101100001010->0\n101100001011->0\n101100001100->0\n101100001101->0\n101100001110->0\n101100001111->0\n101100010000->0\n101100010001->0\n101100010010->0\n101100010011->0\n101100010100->0\n101100010101->0\n101100010110->0\n101100010111->0\n101100011000->0\n101100011001->0\n101100011010->0\n101100011011->0\n101100011100->0\n101100011101->0\n101100011110->0\n101100011111->0\n110000000000->0\n110000000010->0\n110000000011->0\n110000000100->0\n110000000101->0\n110000000110->0\n110000000111->0\n110000001000->0\n110000001001->0\n110000001010->0\n110000001011->0\n110000001100->0\n110000001101->0\n110000001110->0\n110000001111->0\n110000010000->0\n110000010001->0\n110000010010->0\n110000010011->0\n110000010100->0\n110000010101->0\n110000010110->0\n110000010111->0\n110000011000->0\n110000011001->0\n110000011010->0\n110000011011->0\n110000011100->0\n110000011101->0\n110000011110->0\n110000011111->0\n111100010001->0\n111100010010->0\n111100010011->0\n111100010100->0\n111100010101->0\n ?",
|
|
"minimizedTable":"000?????????->1\n ?"
|
|
},
|
|
{
|
|
"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
|
|
"target":"~VCU118RocketSystem|CSRFile>io_decode_0_vector_csr_plaOutput",
|
|
"truthTable":"000000000001->0\n000000000010->0\n000000000011->0\n001100000000->0\n001100000001->0\n001100000100->0\n001100000101->0\n001100100000->0\n001100100011->0\n001100100100->0\n001100100101->0\n001100100110->0\n001100100111->0\n001100101000->0\n001100101001->0\n001100101010->0\n001100101011->0\n001100101100->0\n001100101101->0\n001100101110->0\n001100101111->0\n001100110000->0\n001100110001->0\n001100110010->0\n001100110011->0\n001100110100->0\n001100110101->0\n001100110110->0\n001100110111->0\n001100111000->0\n001100111001->0\n001100111010->0\n001100111011->0\n001100111100->0\n001100111101->0\n001100111110->0\n001100111111->0\n001101000000->0\n001101000001->0\n001101000010->0\n001101000011->0\n001101000100->0\n001110100000->0\n001110100010->0\n001110110000->0\n001110110001->0\n001110110010->0\n001110110011->0\n001110110100->0\n001110110101->0\n001110110110->0\n001110110111->0\n001110111000->0\n001110111001->0\n001110111010->0\n001110111011->0\n001110111100->0\n001110111101->0\n001110111110->0\n001110111111->0\n011110100000->0\n011110100001->0\n011110100010->0\n011110100011->0\n011110110000->0\n011110110001->0\n011110110010->0\n011111000001->0\n101100000000->0\n101100000010->0\n101100000011->0\n101100000100->0\n101100000101->0\n101100000110->0\n101100000111->0\n101100001000->0\n101100001001->0\n101100001010->0\n101100001011->0\n101100001100->0\n101100001101->0\n101100001110->0\n101100001111->0\n101100010000->0\n101100010001->0\n101100010010->0\n101100010011->0\n101100010100->0\n101100010101->0\n101100010110->0\n101100010111->0\n101100011000->0\n101100011001->0\n101100011010->0\n101100011011->0\n101100011100->0\n101100011101->0\n101100011110->0\n101100011111->0\n110000000000->0\n110000000010->0\n110000000011->0\n110000000100->0\n110000000101->0\n110000000110->0\n110000000111->0\n110000001000->0\n110000001001->0\n110000001010->0\n110000001011->0\n110000001100->0\n110000001101->0\n110000001110->0\n110000001111->0\n110000010000->0\n110000010001->0\n110000010010->0\n110000010011->0\n110000010100->0\n110000010101->0\n110000010110->0\n110000010111->0\n110000011000->0\n110000011001->0\n110000011010->0\n110000011011->0\n110000011100->0\n110000011101->0\n110000011110->0\n110000011111->0\n111100010001->0\n111100010010->0\n111100010011->0\n111100010100->0\n111100010101->0\n ?",
|
|
"minimizedTable":"????????????->0\n ?"
|
|
},
|
|
{
|
|
"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
|
|
"target":"~VCU118RocketSystem|CSRFile>io_decode_0_read_illegal_plaOutput",
|
|
"truthTable":"000000000001->0\n000000000010->0\n000000000011->0\n001100000000->0\n001100000001->0\n001100000100->0\n001100000101->0\n001100100000->0\n001100100011->0\n001100100100->0\n001100100101->0\n001100100110->0\n001100100111->0\n001100101000->0\n001100101001->0\n001100101010->0\n001100101011->0\n001100101100->0\n001100101101->0\n001100101110->0\n001100101111->0\n001100110000->0\n001100110001->0\n001100110010->0\n001100110011->0\n001100110100->0\n001100110101->0\n001100110110->0\n001100110111->0\n001100111000->0\n001100111001->0\n001100111010->0\n001100111011->0\n001100111100->0\n001100111101->0\n001100111110->0\n001100111111->0\n001101000000->0\n001101000001->0\n001101000010->0\n001101000011->0\n001101000100->0\n001110100000->0\n001110100010->0\n001110110000->0\n001110110001->0\n001110110010->0\n001110110011->0\n001110110100->0\n001110110101->0\n001110110110->0\n001110110111->0\n001110111000->0\n001110111001->0\n001110111010->0\n001110111011->0\n001110111100->0\n001110111101->0\n001110111110->0\n001110111111->0\n011110100000->0\n011110100001->0\n011110100010->0\n011110100011->0\n011110110000->1\n011110110001->1\n011110110010->1\n011111000001->0\n101100000000->0\n101100000010->0\n101100000011->0\n101100000100->0\n101100000101->0\n101100000110->0\n101100000111->0\n101100001000->0\n101100001001->0\n101100001010->0\n101100001011->0\n101100001100->0\n101100001101->0\n101100001110->0\n101100001111->0\n101100010000->0\n101100010001->0\n101100010010->0\n101100010011->0\n101100010100->0\n101100010101->0\n101100010110->0\n101100010111->0\n101100011000->0\n101100011001->0\n101100011010->0\n101100011011->0\n101100011100->0\n101100011101->0\n101100011110->0\n101100011111->0\n110000000000->0\n110000000010->0\n110000000011->0\n110000000100->0\n110000000101->0\n110000000110->0\n110000000111->0\n110000001000->0\n110000001001->0\n110000001010->0\n110000001011->0\n110000001100->0\n110000001101->0\n110000001110->0\n110000001111->0\n110000010000->0\n110000010001->0\n110000010010->0\n110000010011->0\n110000010100->0\n110000010101->0\n110000010110->0\n110000010111->0\n110000011000->0\n110000011001->0\n110000011010->0\n110000011011->0\n110000011100->0\n110000011101->0\n110000011110->0\n110000011111->0\n111100010001->0\n111100010010->0\n111100010011->0\n111100010100->0\n111100010101->0\n ?",
|
|
"minimizedTable":"01111011????->1\n ?"
|
|
},
|
|
{
|
|
"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
|
|
"target":"~VCU118RocketSystem|CSRFile>io_decode_0_read_illegal_plaOutput_1",
|
|
"truthTable":"000000000001->0\n000000000010->0\n000000000011->0\n001100000000->0\n001100000001->0\n001100000100->0\n001100000101->0\n001100100000->0\n001100100011->0\n001100100100->0\n001100100101->0\n001100100110->0\n001100100111->0\n001100101000->0\n001100101001->0\n001100101010->0\n001100101011->0\n001100101100->0\n001100101101->0\n001100101110->0\n001100101111->0\n001100110000->0\n001100110001->0\n001100110010->0\n001100110011->0\n001100110100->0\n001100110101->0\n001100110110->0\n001100110111->0\n001100111000->0\n001100111001->0\n001100111010->0\n001100111011->0\n001100111100->0\n001100111101->0\n001100111110->0\n001100111111->0\n001101000000->0\n001101000001->0\n001101000010->0\n001101000011->0\n001101000100->0\n001110100000->0\n001110100010->0\n001110110000->0\n001110110001->0\n001110110010->0\n001110110011->0\n001110110100->0\n001110110101->0\n001110110110->0\n001110110111->0\n001110111000->0\n001110111001->0\n001110111010->0\n001110111011->0\n001110111100->0\n001110111101->0\n001110111110->0\n001110111111->0\n011110100000->0\n011110100001->0\n011110100010->0\n011110100011->0\n011110110000->0\n011110110001->0\n011110110010->0\n011111000001->0\n101100000000->0\n101100000010->0\n101100000011->0\n101100000100->0\n101100000101->0\n101100000110->0\n101100000111->0\n101100001000->0\n101100001001->0\n101100001010->0\n101100001011->0\n101100001100->0\n101100001101->0\n101100001110->0\n101100001111->0\n101100010000->0\n101100010001->0\n101100010010->0\n101100010011->0\n101100010100->0\n101100010101->0\n101100010110->0\n101100010111->0\n101100011000->0\n101100011001->0\n101100011010->0\n101100011011->0\n101100011100->0\n101100011101->0\n101100011110->0\n101100011111->0\n110000000000->0\n110000000010->0\n110000000011->0\n110000000100->0\n110000000101->0\n110000000110->0\n110000000111->0\n110000001000->0\n110000001001->0\n110000001010->0\n110000001011->0\n110000001100->0\n110000001101->0\n110000001110->0\n110000001111->0\n110000010000->0\n110000010001->0\n110000010010->0\n110000010011->0\n110000010100->0\n110000010101->0\n110000010110->0\n110000010111->0\n110000011000->0\n110000011001->0\n110000011010->0\n110000011011->0\n110000011100->0\n110000011101->0\n110000011110->0\n110000011111->0\n111100010001->0\n111100010010->0\n111100010011->0\n111100010100->0\n111100010101->0\n ?",
|
|
"minimizedTable":"????????????->0\n ?"
|
|
},
|
|
{
|
|
"class":"chisel3.util.experimental.decode.DecodeTableAnnotation",
|
|
"target":"~VCU118RocketSystem|MulDiv>decoded",
|
|
"truthTable":"000->10??\n001->1111\n010->1110\n011->1100\n100->0011\n101->0000\n110->0111\n111->0100\n ????",
|
|
"minimizedTable":"??0->??1?\n0??->1???\n00?->??11\n0?1->?1??\n?1?->?1??\n1?0->???1\n ????"
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.BlackBoxInlineAnno",
|
|
"target":"VCU118RocketSystem.plusarg_reader",
|
|
"name":"plusarg_reader.v",
|
|
"text":"// See LICENSE.SiFive for license details.\n\n//VCS coverage exclude_file\n\n// No default parameter values are intended, nor does IEEE 1800-2012 require them (clause A.2.4 param_assignment),\n// but Incisive demands them. These default values should never be used.\nmodule plusarg_reader #(\n parameter FORMAT=\"borked=%d\",\n parameter WIDTH=1,\n parameter [WIDTH-1:0] DEFAULT=0\n) (\n output [WIDTH-1:0] out\n);\n\n`ifdef SYNTHESIS\nassign out = DEFAULT;\n`else\nreg [WIDTH-1:0] myplus;\nassign out = myplus;\n\ninitial begin\n if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;\nend\n`endif\n\nendmodule\n"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.HierarchicalElementResetDomain"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.FixedClockBroadcast_1_1"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.IntXbar_i1_o1"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.IntXbar_i1_o1_1"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.IntXbar_i1_o1_2"
|
|
},
|
|
{
|
|
"class":"firrtl.transforms.DontTouchAnnotation",
|
|
"target":"~VCU118RocketSystem|BundleBridgeNexus_UInt1_2>outputs_0"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.BundleBridgeNexus_UInt32_1"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.BundleBridgeNexus_TraceBundle"
|
|
},
|
|
{
|
|
"class":"firrtl.passes.InlineAnnotation",
|
|
"target":"VCU118RocketSystem.BundleBridgeNexus_TraceCoreInterface"
|
|
}
|
|
] |