33 lines
1.0 KiB
INI
33 lines
1.0 KiB
INI
# Rocket debug through the Ti375 hard TAP, JTAG_USER1, and the project's DMI tunnel.
|
|
|
|
adapter driver ftdi
|
|
ftdi vid_pid 0x0403 0x6011
|
|
ftdi channel 1
|
|
ftdi layout_init 0x08 0x0b
|
|
|
|
if {![info exists ADAPTER_SPEED]} {
|
|
set ADAPTER_SPEED 1000
|
|
}
|
|
adapter speed $ADAPTER_SPEED
|
|
|
|
jtag newtap ti375 fpga -expected-id 0x006A0A79 -irlen 5 -ircapture 0x5 -irmask 0xF
|
|
target create rocket.cpu riscv -chain-position ti375.fpga -coreid 0
|
|
|
|
# The outer Ti375 USER1 instruction is 0x08. The inner tunnel implements the
|
|
# same 5-bit Rocket DTM IR and framing used by the Xilinx targets.
|
|
riscv set_ir dtmcs 0x10
|
|
riscv set_ir dmi 0x11
|
|
riscv use_bscan_tunnel 5 0
|
|
# Ti375 requires an OpenOCD build with the upstream configurable outer BSCAN
|
|
# instruction support. Keep the catch only so older builds produce a readable
|
|
# diagnostic before their legacy Xilinx-specific BSCAN path rejects this TAP.
|
|
if {[catch {riscv set_bscan_tunnel_ir 8}]} {
|
|
echo "OpenOCD lacks 'riscv set_bscan_tunnel_ir'; Ti375 requires that command"
|
|
}
|
|
|
|
riscv set_reset_timeout_sec 10
|
|
riscv set_command_timeout_sec 10
|
|
|
|
init
|
|
halt
|