58 lines
2.0 KiB
Systemverilog
58 lines
2.0 KiB
Systemverilog
module butterfly #(
|
|
parameter DATA_WIDTH = 4,
|
|
parameter FFT_POWER = 4,
|
|
parameter TWIDDLE_WIDTH = 15,
|
|
parameter FRAC_BITS = 2
|
|
)
|
|
(
|
|
input logic clk,
|
|
input logic [FFT_POWER-2 : 0] k_i,
|
|
input logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] x0_real_i,
|
|
input logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] x0_imag_i,
|
|
input logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] x1_real_i,
|
|
input logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] x1_imag_i,
|
|
|
|
output logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y0_real_o,
|
|
output logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y0_imag_o,
|
|
output logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y1_real_o,
|
|
output logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y1_imag_o
|
|
);
|
|
|
|
logic signed [TWIDDLE_WIDTH-1 : 0] tw_real;
|
|
logic signed [TWIDDLE_WIDTH-1 : 0] tw_imag;
|
|
|
|
logic signed [DATA_WIDTH + FFT_POWER + TWIDDLE_WIDTH + FRAC_BITS : 0] x1_real_w;
|
|
logic signed [DATA_WIDTH + FFT_POWER + TWIDDLE_WIDTH + FRAC_BITS : 0] x1_imag_w;
|
|
|
|
logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y0_real;
|
|
logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y0_imag;
|
|
logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y1_real;
|
|
logic signed [FRAC_BITS + DATA_WIDTH + FFT_POWER - 1 : 0] y1_imag;
|
|
|
|
twiddle_ram #(
|
|
.TWIDDLE_WIDTH(TWIDDLE_WIDTH),
|
|
.FFT_POWER(FFT_POWER)
|
|
)
|
|
twiddle_ram_i(
|
|
.clk(clk),
|
|
.addr_i(k_i),
|
|
.tw_real_o(tw_real),
|
|
.tw_imag_o(tw_imag)
|
|
);
|
|
|
|
assign x1_real_w = (x1_real_i * tw_real - x1_imag_i * tw_imag) >>> (TWIDDLE_WIDTH-2);
|
|
assign x1_imag_w = (x1_imag_i * tw_real + x1_real_i * tw_imag) >>> (TWIDDLE_WIDTH-2);
|
|
|
|
assign y0_real = x0_real_i + x1_real_w;
|
|
assign y0_imag = x0_imag_i + x1_imag_w;
|
|
|
|
assign y1_real = x0_real_i - x1_real_w;
|
|
assign y1_imag = x0_imag_i - x1_imag_w;
|
|
|
|
assign y0_real_o = y0_real;
|
|
assign y0_imag_o = y0_imag;
|
|
assign y1_real_o = y1_real;
|
|
assign y1_imag_o = y1_imag;
|
|
|
|
endmodule
|