127 lines
3.3 KiB
Systemverilog
127 lines
3.3 KiB
Systemverilog
//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 01/08/2024 12:56:23 PM
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// Design Name:
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// Module Name: gps_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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import definitions::*;
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module gps_top(
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input logic arstn,
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input logic acq_clk,
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input logic trk_clk,
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input logic afe_clk,
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input logic [RF_DATA_WIDTH-1 : 0] rf_data_i,
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input logic afe_start_i,
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input logic sample_counter_clear_i,
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input logic acq_start_i,
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input logic [PRN_WL-1 : 0] acq_prn_i,
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input trck_i_struct_t trck_i [0 : NUM_TRCK_CH-1],
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output acq_o_struct_t acq_o,
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output trck_o_struct_t trck_o [0 : NUM_TRCK_CH-1]
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);
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logic afe_rstn, acq_rstn, trk_rstn;
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logic sample_align;
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logic [ABS_SAMPLE_CNTR_WL-1:0] sample_counter;
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reset_synch reset_synch_i(
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.arstn_i(arstn),
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.afe_clk(afe_clk),
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.acq_clk(acq_clk),
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.trk_clk(trk_clk),
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.afe_rstn_o(afe_rstn),
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.acq_rstn_o(acq_rstn),
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.trk_rstn_o(trk_rstn)
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);
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afe_top afe_top_i(
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.afe_rstn(afe_rstn),
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.trk_rstn(trk_rstn),
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.afe_clk(afe_clk),
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.trk_clk(trk_clk),
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.start_i(afe_start_i),
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.sample_counter_clear_i(sample_counter_clear_i),
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.sample_align_o(sample_align),
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.sample_counter_o(sample_counter)
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);
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acq_top acq_top_i (
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.acq_rstn(acq_rstn),
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.afe_rstn(afe_rstn),
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.acq_clk(acq_clk),
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.afe_clk(afe_clk),
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.rf_data_i(rf_data_i),
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.sample_align_i(sample_align),
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.start_i(acq_start_i),
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.prn_i(acq_prn_i),
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.end_o(acq_o.end_o),
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.status_o(acq_o.status),
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.busy_o(acq_o.busy),
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.peak_metric_o(acq_o.peak_metric),
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.code_phase_o(acq_o.code_phase),
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.carr_freq_o(acq_o.carr_freq)
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);
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genvar ch;
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generate
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for (ch=0; ch < NUM_TRCK_CH; ch++) begin
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trck_top trck_top_i (
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.trk_rstn (trk_rstn),
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.afe_rstn (afe_rstn),
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.trk_clk (trk_clk),
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.afe_clk (afe_clk),
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.rf_data_i (rf_data_i),
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.sample_align_i (sample_align),
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.sample_counter_i (sample_counter),
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.start_i (trck_i[ch].start),
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.stop_i (trck_i[ch].stop),
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.prn_i (trck_i[ch].prn),
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.carr_freq_i (trck_i[ch].carr_freq),
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.code_phase_i (trck_i[ch].code_phase),
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.bit_o (trck_o[ch].bit_o),
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.bit_vld_o (trck_o[ch].bit_vld),
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.abs_sample_o (trck_o[ch].abs_sample),
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.rem_code_ph_o (),
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.measurement_vld_o (),
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.measurement_bit_o (),
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.measurement_abs_sample_o(),
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.measurement_rem_code_ph_o(),
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.measurement_carrier_freq_q7_o(),
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.measurement_cn0_sum_i_o(),
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.measurement_cn0_sum_q_o(),
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.measurement_cn0_wbp_o(),
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.measurement_cn0_sample_count_o(),
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.measurement_sequence_o(),
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.fifo_of_o (), //reserved
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.lock_o (trck_o[ch].lock),
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.busy_o (trck_o[ch].busy)
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);
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end
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endgenerate
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endmodule
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