19 lines
510 B
Makefile
19 lines
510 B
Makefile
.PHONY: help all shell generated clean
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help:
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@echo "Genesys2 RTL targets:"
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@echo " make shell # list hand-written FPGA shell RTL"
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@echo " make generated # generate Rocket SystemVerilog and wrapper"
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@echo " make clean # remove generated wrapper/verilog"
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all: generated
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shell:
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@find . -type f -name '*.sv' -print | sort
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generated:
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@make -C ../../../../targets/fpga/genesys2 rtl
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clean:
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rm -rf ../../../generated/genesys2-soc-verilog ../../../../targets/fpga/genesys2/out/build/generated
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