This flow builds the same Rocket SoC for an ASIC-style shell: no FPGA clock, startup, BSCAN, or flash access primitives are instantiated. The top level uses plain clock/reset, UART, SPI, and JTAG pins.

Commands

The ASIC flow is driven directly by this directory's Makefile; there is no separate flow dispatcher script.

make -C targets/asic/rocket rtl
make -C targets/asic/rocket sim-rtl
make -C targets/asic/rocket vlog-soc
make -C targets/asic/rocket vlog-tb
make -C targets/asic/rocket sim
make -C targets/asic/rocket sim-pmod-irq
make -C targets/asic/rocket sim-pmod-irq-rtl
make -C targets/asic/rocket sim GUI=1

The default simulation app is hello_uart.

The ASIC Makefile always checks the bootloader build configuration before hardware generation. This prevents a previously built Genesys2 image (50 MHz UART and a different flash offset) from being silently embedded in the ASIC BootROM; the ASIC defaults are 100 MHz, 115200 baud, and flash offset 0x06000000.

sim-pmod-irq drives the ASIC top-level pmod_irq input with four asynchronous square-wave periods, checks that TLPLIC source 10 becomes pending (architectural device ID 11), and boots the standalone pmod_irq_test firmware. PASS therefore requires both the RTL pending bit and a successful CPU PLIC interrupt/ISR return; a pin toggle alone is not accepted.

sim-pmod-irq-rtl applies the same four asynchronous periods but finishes as soon as all four input rising edges and the PLIC device-11 pending state have been observed. It skips the slow bootloader/SPI-flash/firmware phase and is the fast regression for the ASIC input-to-PLIC hardware route. It does not claim to test the C interrupt handler; use sim-pmod-irq for that end-to-end check.

PMOD IRQ ASIC simulation result

Verified on 2026-07-14 with QuestaSim 2021.2_1:

ASIC PMOD IRQ: PLIC device 11 pending observed
UART: Flash JEDEC ID: 0x0020bb21
UART: Load: flash 0x06000040 -> mem 0x80000000, size 0x00000908
UART: CRC ok, jumping 0x80000000
C main returned 0
ASIC PMOD IRQ PASS: rises=4 pending_seen=1
ASIC sanity PASS
Errors: 0

The fast RTL-only regression also passed at simulation time 1455 ns with four rising edges and PLIC device 11 pending. The full test completed at simulation time 50,972,035 ns. In pmod_irq_test, return code zero is emitted only after the expected device-11 ISR increments its interrupt counter.

make -C targets/asic/rocket sim GUI=1 opens the Questa/ModelSim graphical simulator, loads asic_rocket_tb with -voptargs="+acc", sources hardware/sim/asic/rocket/wave.do, sets onfinish stop, and runs only 0 ns so the GUI is ready for manual waveform/debug work.

Generated outputs:

soc/out/software/: common bootloader and application ELF/img outputs.
soc/out/flash/hello_uart.flash.hex: SPI flash model contents loaded at 0x06000000.
hardware/generated/asic-rocket-soc/: FIRRTL, DTS, memory map.
hardware/generated/asic-rocket-soc-verilog/: synthesis-style split SystemVerilog.
hardware/generated/asic-rocket-soc-sim-verilog/: simulation split SystemVerilog with init blocks.
targets/asic/rocket/out/generated/asic_rocket_top.sv: generic ASIC top.
targets/asic/rocket/out/generated/asic_rocket_top_sim.sv: generic ASIC top for simulation RTL.
targets/asic/rocket/out/filelists/asic_rtl.f: RTL compile filelist.
targets/asic/rocket/out/filelists/asic_tb.f: RTL + SimJTAG + models + testbench filelist.
hardware/sim/asic/rocket/tb/: ASIC testbench and behavioral models.

The ASIC config is freechips.rocketchip.fpga.VCU118RocketJtagConfig; it uses JTAG debug export so the testbench can instantiate SimJTAG.

rtl keeps FIRRTL/CIRCT randomization disabled for synthesis-style output. sim-rtl, vlog-tb, and sim use deterministic simulation init defines so Rocket registers that are intentionally not reset come up as concrete 0/1 values instead of propagating RTL X values. The UART console model prints decoded UART characters to the simulator transcript.

The flash image path can be overridden at simulation runtime with:

+flash_hex=/path/to/image.hex