53 lines
1.4 KiB
Makefile
53 lines
1.4 KiB
Makefile
.PHONY: help all bitstream program program-fpga flash-app flash-bitstream flash-combined debug-openocd debug-load debug-gdb uart-listen fpga-config prune clean
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help:
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@echo "Genesys2 FPGA targets:"
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@echo " make bitstream # run Vivado non-project build"
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@echo " make program # program FPGA SRAM with current bitstream"
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@echo " make flash-app # program only app/ELF flash region"
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@echo " make flash-bitstream # program bitstream flash region"
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@echo " make flash-combined # old one-MCS flash flow"
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@echo " make debug-openocd # OpenOCD BSCAN/GDB server"
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@echo " make debug-load # load APP over GDB and run"
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@echo " make uart-listen # listen to board UART"
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@echo " make fpga-config # show board clocks, flash, UART, and Vivado config"
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@echo " make prune # remove bulky temporary outputs"
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all: bitstream
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bitstream:
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@make -C ../.. bitstream
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program program-fpga:
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@make -C ../.. program-fpga
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flash-app:
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@make -C ../.. program-flash
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flash-bitstream:
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@make -C ../.. program-flash-bitstream
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flash-combined:
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@make -C ../.. program-flash-combined
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debug-openocd:
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@make -C ../.. debug-openocd
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debug-load:
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@make -C ../.. debug-load
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debug-gdb:
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@make -C ../.. debug-gdb
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uart-listen:
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@make -C ../.. uart-listen
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fpga-config:
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@make -C ../.. fpga-config
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prune:
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@make -C ../.. prune
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clean:
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@make -C ../.. clean-fpga
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