282 lines
13 KiB
TableGen
282 lines
13 KiB
TableGen
//===- IntrinsicsRISCVXsf.td - SiFive intrinsics -----------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the SiFive vendor intrinsics for RISC-V.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "riscv" in {
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// Output: (vector_out)
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// Input: (bit<27-26>, bit<24-20>, scalar_in, vl) or
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class RISCVSFCustomVC_X<bit HasSE, bit ImmScalar>
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: Intrinsic<[llvm_anyvector_ty],
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[llvm_anyint_ty, LLVMMatchType<1>, llvm_any_ty, llvm_anyint_ty],
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!listconcat([IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>], // bit<27-26> and bit<24-20>
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!if(ImmScalar, [ImmArg<ArgIndex<2>>], []), // ScalarOperand
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!if(HasSE, [IntrHasSideEffects], []))>,
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RISCVVIntrinsic {
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let ScalarOperand = !cond(ImmScalar: NoScalarOperand,
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true: 2);
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let VLOperand = 3;
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}
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// Output: ()
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// Input: (bit<27-26>, bit<24-20>, bit<11-7>, scalar_in, sew, log2lmul, vl)
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class RISCVSFCustomVC_X_WO_Suffix<bit ImmScalar>
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: Intrinsic<[],
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[llvm_anyint_ty, LLVMMatchType<0>, LLVMMatchType<0>,
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llvm_any_ty, LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty],
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!listconcat([IntrNoMem, IntrHasSideEffects, ImmArg<ArgIndex<0>>,
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ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>,
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ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>], // bit<27-26>, bit<24-20>, bit<11-7>, sew, log2lmul
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!if(ImmScalar, [ImmArg<ArgIndex<3>>], []))>, // ScalarOperand
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RISCVVIntrinsic {
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let ScalarOperand = !cond(ImmScalar: NoScalarOperand,
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true: 3);
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let VLOperand = 6;
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}
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// Output: (vector_out) or ()
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// Input: (bit<27-26>, vector_in, vector_in/scalar_in, vl) or
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// (bit<27-26>, bit<11-7>, vector_in, vector_in/scalar_in, vl)
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class RISCVSFCustomVC_XV<bit HasDst, bit HasSE, bit ImmScalar>
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: Intrinsic<!if(HasDst, [llvm_anyvector_ty], []),
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!listconcat(!if(HasDst, [llvm_anyint_ty, llvm_anyvector_ty],
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[llvm_anyint_ty, LLVMMatchType<0>, llvm_anyvector_ty]),
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[llvm_any_ty, llvm_anyint_ty]),
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!listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
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!if(HasDst, [], [ImmArg<ArgIndex<1>>]), // Vd or bit<11-7>
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!if(ImmScalar, !if(HasDst, [ImmArg<ArgIndex<2>>],
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[ImmArg<ArgIndex<3>>]), []), // ScalarOperand
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!if(HasSE, [IntrHasSideEffects], []))>,
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RISCVVIntrinsic {
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let ScalarOperand = !cond(ImmScalar: NoScalarOperand,
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HasDst: 2,
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true: 3);
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let VLOperand = !if(HasDst, 3, 4);
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}
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// Output: (vector_out) or ()
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// Input: (bit<27-26>, passthru, vector_in, vector_in/scalar_in, vl) or
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// (bit<27-26>, vector_in, vector_in, vector_in/scalar_in, vl)
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class RISCVSFCustomVC_XVV<bit HasDst, bit HasSE, bit ImmScalar>
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: Intrinsic<!if(HasDst, [llvm_anyvector_ty], []),
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!listconcat(!if(HasDst, [llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty],
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[llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty]),
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[llvm_any_ty, llvm_anyint_ty]),
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!listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
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!if(ImmScalar, [ImmArg<ArgIndex<3>>], []), // ScalarOperand
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!if(HasSE, [IntrHasSideEffects], []))>,
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RISCVVIntrinsic {
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let ScalarOperand = !if(ImmScalar, NoScalarOperand, 3);
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let VLOperand = 4;
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}
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// Output: (wvector_out) or ()
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// Input: (bit<27-26>, passthru, vector_in, vector_in/scalar_in, vl) or
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// (bit<27-26>, wvector_in, vector_in, vector_in/scalar_in, vl)
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class RISCVSFCustomVC_XVW<bit HasDst, bit HasSE, bit ImmScalar>
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: Intrinsic<!if(HasDst, [llvm_anyvector_ty], []),
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!listconcat(!if(HasDst, [llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty],
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[llvm_anyint_ty, llvm_anyvector_ty, llvm_anyvector_ty]),
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[llvm_any_ty, llvm_anyint_ty]),
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!listconcat([IntrNoMem, ImmArg<ArgIndex<0>>], // bit<27-26>
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!if(ImmScalar, [ImmArg<ArgIndex<3>>], []), // ScalarOperand
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!if(HasSE, [IntrHasSideEffects], []))>,
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RISCVVIntrinsic {
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let ScalarOperand = !if(ImmScalar, NoScalarOperand, 3);
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let VLOperand = 4;
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}
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multiclass RISCVSFCustomVC_X<list<string> type> {
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foreach t = type in {
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defvar ImmScalar = !eq(t, "i");
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def "int_riscv_sf_vc_" # t # "_se" : RISCVSFCustomVC_X_WO_Suffix<ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "_se" : RISCVSFCustomVC_X<HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t : RISCVSFCustomVC_X<HasSE=0, ImmScalar=ImmScalar>;
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}
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}
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multiclass RISCVSFCustomVC_XV<list<string> type> {
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foreach t = type in {
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defvar ImmScalar = !eq(t, "i");
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def "int_riscv_sf_vc_" # t # "v_se" : RISCVSFCustomVC_XV<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "v_se" : RISCVSFCustomVC_XV<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "v" : RISCVSFCustomVC_XV<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;
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}
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}
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multiclass RISCVSFCustomVC_XVV<list<string> type> {
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foreach t = type in {
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defvar ImmScalar = !eq(t, "i");
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def "int_riscv_sf_vc_" # t # "vv_se" : RISCVSFCustomVC_XVV<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "vv_se" : RISCVSFCustomVC_XVV<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "vv" : RISCVSFCustomVC_XVV<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;
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}
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}
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multiclass RISCVSFCustomVC_XVW<list<string> type> {
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foreach t = type in {
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defvar ImmScalar = !eq(t, "i");
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def "int_riscv_sf_vc_" # t # "vw_se" : RISCVSFCustomVC_XVW<HasDst=0, HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "vw_se" : RISCVSFCustomVC_XVW<HasDst=1, HasSE=1, ImmScalar=ImmScalar>;
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def "int_riscv_sf_vc_v_" # t # "vw" : RISCVSFCustomVC_XVW<HasDst=1, HasSE=0, ImmScalar=ImmScalar>;
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}
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}
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class RISCVSFCustomVMACC
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: DefaultAttrsIntrinsic< [llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, llvm_anyvector_ty,
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llvm_anyint_ty, LLVMMatchType<3>],
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[ImmArg<ArgIndex<4>>, IntrNoMem] >, RISCVVIntrinsic {
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let VLOperand = 3;
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}
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// Input: (passthru, vector_in, scalar_in, frm, vl)
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class RISCVSFCustomVFNRCLIPUnMasked
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyfloat_ty, LLVMVectorElementType<1>,
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llvm_anyint_ty, LLVMMatchType<2>],
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[ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
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let VLOperand = 4;
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}
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// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
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class RISCVSFCustomVFNRCLIPMasked
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyfloat_ty, LLVMVectorElementType<1>,
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LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
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LLVMMatchType<2>, LLVMMatchType<2>],
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[ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>, RISCVVIntrinsic {
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let VLOperand = 5;
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}
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multiclass RISCVSFCustomVFNRCLIP {
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def NAME : RISCVSFCustomVFNRCLIPUnMasked;
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def NAME # "_mask" : RISCVSFCustomVFNRCLIPMasked;
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}
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defm "" : RISCVSFCustomVC_X<["x", "i"]>;
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defm "" : RISCVSFCustomVC_XV<["x", "i", "v", "f"]>;
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defm "" : RISCVSFCustomVC_XVV<["x", "i", "v", "f"]>;
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defm "" : RISCVSFCustomVC_XVW<["x", "i", "v", "f"]>;
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// XSfvfexp* and XSfvfexpa*
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defm sf_vfexp : RISCVUnaryAA;
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defm sf_vfexpa : RISCVUnaryAA;
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// XSfvqmaccdod
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def int_riscv_sf_vqmaccu_2x8x2 : RISCVSFCustomVMACC;
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def int_riscv_sf_vqmacc_2x8x2 : RISCVSFCustomVMACC;
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def int_riscv_sf_vqmaccus_2x8x2 : RISCVSFCustomVMACC;
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def int_riscv_sf_vqmaccsu_2x8x2 : RISCVSFCustomVMACC;
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// XSfvqmaccqoq
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def int_riscv_sf_vqmaccu_4x8x4 : RISCVSFCustomVMACC;
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def int_riscv_sf_vqmacc_4x8x4 : RISCVSFCustomVMACC;
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def int_riscv_sf_vqmaccus_4x8x4 : RISCVSFCustomVMACC;
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def int_riscv_sf_vqmaccsu_4x8x4 : RISCVSFCustomVMACC;
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// XSfvfwmaccqqq
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def int_riscv_sf_vfwmacc_4x4x4 : RISCVSFCustomVMACC;
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// XSfvfnrclipxfqf
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defm int_riscv_sf_vfnrclip_x_f_qf : RISCVSFCustomVFNRCLIP;
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defm int_riscv_sf_vfnrclip_xu_f_qf : RISCVSFCustomVFNRCLIP;
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// XSfmm
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// Output: (output_len)
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// Input: (input_len, vsew, twiden)
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class RISCVSFVSet
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: DefaultAttrsIntrinsic<[llvm_anyint_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, IntrNoMem]>;
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// Input: (tss, base, tn)
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class RISCVSFTileLoad
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: DefaultAttrsIntrinsic<[],
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[llvm_anyint_ty, llvm_ptr_ty, LLVMMatchType<0>],
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[NoCapture<ArgIndex<1>>, IntrHasSideEffects]>,
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RISCVVIntrinsic;
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// Input: (tss, base, tn)
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class RISCVSFTileStore
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: DefaultAttrsIntrinsic<[],
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[llvm_anyint_ty, llvm_ptr_ty, LLVMMatchType<0>],
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[NoCapture<ArgIndex<1>>, IntrWriteMem,
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IntrHasSideEffects]>,
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RISCVVIntrinsic;
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// Output: ()
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// Input: (mtd, mat1, mat2, tm, tn, tk, twiden)
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class RISCVSFCustomMatMul<bit is_float = false>
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: DefaultAttrsIntrinsic<[], [llvm_anyint_ty, llvm_anyvector_ty,
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!if(is_float, LLVMMatchType<1>,
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llvm_anyvector_ty),
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LLVMMatchType<0>, LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrHasSideEffects,
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ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<6>>]>,
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RISCVVIntrinsic;
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def int_riscv_sf_vsettnt : RISCVSFVSet;
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def int_riscv_sf_vsettm : RISCVSFVSet;
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def int_riscv_sf_vsettk : RISCVSFVSet;
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def int_riscv_sf_vlte8 : RISCVSFTileLoad;
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def int_riscv_sf_vlte16 : RISCVSFTileLoad;
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def int_riscv_sf_vlte32 : RISCVSFTileLoad;
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def int_riscv_sf_vlte64 : RISCVSFTileLoad;
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def int_riscv_sf_vste8 : RISCVSFTileStore;
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def int_riscv_sf_vste16 : RISCVSFTileStore;
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def int_riscv_sf_vste32 : RISCVSFTileStore;
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def int_riscv_sf_vste64 : RISCVSFTileStore;
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// Output: (vd)
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// Input: (tss, tn)
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def int_riscv_sf_vtmv_v_t
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: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
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[llvm_anyint_ty, LLVMMatchType<1>],
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[IntrNoMem, IntrHasSideEffects]>,
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RISCVVIntrinsic {
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let VLOperand = 2;
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}
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// Output: ()
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// Input: (tss, vs2, tn)
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def int_riscv_sf_vtmv_t_v
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: DefaultAttrsIntrinsic<[], [LLVMMatchType<1>, llvm_anyvector_ty,
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llvm_anyint_ty], [IntrNoMem, IntrHasSideEffects]>,
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RISCVVIntrinsic {
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let VLOperand = 2;
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}
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foreach a = ["u", "s"] in {
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foreach b = ["u", "s"] in {
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def int_riscv_sf_mm_ # a # _ # b : RISCVSFCustomMatMul;
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}
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}
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def int_riscv_sf_mm_f_f : RISCVSFCustomMatMul<true>;
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foreach e1 = [5, 4] in
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foreach e2 = [5, 4] in
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def int_riscv_sf_mm_e # e1 # m # !sub(7, e1) # _e # e2 # m # !sub(7, e2)
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: RISCVSFCustomMatMul<true>;
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// Output: ()
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// Input: (mtd)
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def int_riscv_sf_vtzero_t
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: DefaultAttrsIntrinsic<[],
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[llvm_anyint_ty, LLVMMatchType<0>,LLVMMatchType<0>,
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LLVMMatchType<0>, LLVMMatchType<0>],
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[ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<3>>,
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ImmArg<ArgIndex<4>>, IntrNoMem, IntrHasSideEffects]>,
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RISCVVIntrinsic;
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// Output: ()
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// Input: ()
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def int_riscv_sf_vtdiscard
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: DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>,
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RISCVVIntrinsic;
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} // TargetPrefix = "riscv"
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