223 lines
9.8 KiB
C++
223 lines
9.8 KiB
C++
//===- Passes.h - GPU pipeline entry points--------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_DIALECT_GPU_PIPELINES_PASSES_H_
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#define MLIR_DIALECT_GPU_PIPELINES_PASSES_H_
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#include "mlir/Pass/PassOptions.h"
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namespace mlir {
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namespace gpu {
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/// Options for the gpu to nvvm pipeline.
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struct GPUToNVVMPipelineOptions
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: public PassPipelineOptions<GPUToNVVMPipelineOptions> {
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PassOptions::Option<int64_t> indexBitWidth{
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*this, "index-bitwidth",
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llvm::cl::desc("Bitwidth of the index type for the host (warning this "
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"should be 64 until the GPU layering is fixed)"),
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llvm::cl::init(64)};
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PassOptions::Option<std::string> cubinTriple{
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*this, "cubin-triple",
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llvm::cl::desc("Triple to use to serialize to cubin."),
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llvm::cl::init("nvptx64-nvidia-cuda")};
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PassOptions::Option<std::string> cubinChip{
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*this, "cubin-chip", llvm::cl::desc("Chip to use to serialize to cubin."),
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llvm::cl::init("sm_75")};
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PassOptions::Option<std::string> cubinFeatures{
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*this, "cubin-features",
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llvm::cl::desc("Features to use to serialize to cubin."),
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llvm::cl::init("")};
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PassOptions::Option<std::string> cubinFormat{
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*this, "cubin-format",
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llvm::cl::desc("Compilation format to use to serialize to cubin."),
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llvm::cl::init("fatbin")};
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PassOptions::Option<std::string> cmdOptions{
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*this, "ptxas-cmd-options",
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llvm::cl::desc(
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"Command line options to pass to the downstream compiler."),
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llvm::cl::init("")};
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PassOptions::Option<int> optLevel{
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*this, "opt-level",
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llvm::cl::desc("Optimization level for NVVM compilation"),
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llvm::cl::init(2)};
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PassOptions::Option<bool> kernelUseBarePtrCallConv{
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*this, "kernel-bare-ptr-calling-convention",
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llvm::cl::desc(
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"Whether to use the bareptr calling convention on the kernel "
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"(warning this should be false until the GPU layering is fixed)"),
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llvm::cl::init(false)};
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PassOptions::Option<bool> hostUseBarePtrCallConv{
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*this, "host-bare-ptr-calling-convention",
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llvm::cl::desc(
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"Whether to use the bareptr calling convention on the host (warning "
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"this should be false until the GPU layering is fixed)"),
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llvm::cl::init(false)};
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PassOptions::Option<bool> allowPatternRollback{
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*this, "allow-pattern-rollback",
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llvm::cl::desc("Allow pattern rollback during dialect conversion"),
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llvm::cl::init(true)};
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};
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/// Options for the gpu to rocdl pipeline.
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struct GPUToROCDLPipelineOptions
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: public PassPipelineOptions<GPUToROCDLPipelineOptions> {
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PassOptions::Option<int64_t> indexBitWidth{
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*this, "index-bitwidth",
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llvm::cl::desc("Bitwidth of the index type for the host (warning this "
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"should be 64 until the GPU layering is fixed)"),
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llvm::cl::init(64)};
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PassOptions::Option<std::string> triple{
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*this, "triple",
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llvm::cl::desc("AMDGPU target triple (e.g. amdgcn-amd-amdhsa)."),
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llvm::cl::init("amdgcn-amd-amdhsa")};
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PassOptions::Option<std::string> chip{
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*this, "chip",
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llvm::cl::desc(
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"AMDGPU target chip (e.g. gfx90a, gfx942, gfx1100). Required: "
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"AMDGCN binaries are not forward-compatible across chip families.")};
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PassOptions::Option<std::string> features{
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*this, "features", llvm::cl::desc("AMDGPU target features."),
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llvm::cl::init("")};
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PassOptions::Option<std::string> binaryFormat{
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*this, "binary-format",
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llvm::cl::desc("Final GPU binary emission format (e.g. fatbin, binary, "
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"isa, llvm, offloading)."),
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llvm::cl::init("fatbin")};
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PassOptions::Option<std::string> abiVersion{
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*this, "abi",
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llvm::cl::desc("AMDHSA ABI version (e.g. \"500\", \"600\")."),
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llvm::cl::init("600")};
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PassOptions::Option<bool> wave64{
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*this, "wave64",
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llvm::cl::desc("Use Wave64 mode (default true; wave32 if false, "
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"appropriate for RDNA / gfx10+ where supported)."),
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llvm::cl::init(true)};
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PassOptions::Option<int> optLevel{
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*this, "opt-level",
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llvm::cl::desc("Optimization level for ROCDL/AMDGPU compilation."),
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llvm::cl::init(2)};
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PassOptions::Option<std::string> cmdOptions{
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*this, "rocdl-cmd-options",
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llvm::cl::desc(
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"Command line options to pass to the downstream AMDGPU compiler."),
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llvm::cl::init("")};
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PassOptions::Option<bool> kernelUseBarePtrCallConv{
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*this, "kernel-bare-ptr-calling-convention",
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llvm::cl::desc("Use bareptr calling convention for device kernels."),
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llvm::cl::init(false)};
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PassOptions::Option<bool> hostUseBarePtrCallConv{
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*this, "host-bare-ptr-calling-convention",
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llvm::cl::desc("Use bareptr calling convention for the host."),
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llvm::cl::init(false)};
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};
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// Options for the gpu to xevm pipeline.
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struct GPUToXeVMPipelineOptions
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: public PassPipelineOptions<GPUToXeVMPipelineOptions> {
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PassOptions::Option<std::string> xegpuOpLevel{
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*this, "xegpu-op-level",
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llvm::cl::desc("Granularity of XeGPU operations to target: workgroup | "
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"subgroup | lane"),
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llvm::cl::init("workgroup")};
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// General lowering controls.
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PassOptions::Option<bool> use64bitIndex{
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*this, "use-64bit-index",
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llvm::cl::desc("Bitwidth of the index type (host & device)"),
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llvm::cl::init(true)};
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PassOptions::Option<bool> kernelBarePtrCallConv{
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*this, "kernel-bare-ptr-calling-convention",
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llvm::cl::desc("Use bare pointer calling convention for device kernels"),
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llvm::cl::init(false)};
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PassOptions::Option<bool> hostBarePtrCallConv{
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*this, "host-bare-ptr-calling-convention",
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llvm::cl::desc("Use bare pointer calling convention for host launches"),
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llvm::cl::init(false)};
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PassOptions::Option<std::string> binaryFormat{
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*this, "binary-format",
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llvm::cl::desc("Final GPU binary emission format (e.g. fatbin)"),
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llvm::cl::init("fatbin")};
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// Options mirroring xevm-attach-target (GpuXeVMAttachTarget).
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PassOptions::Option<std::string> xevmModuleMatcher{
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*this, "xevm-module-matcher",
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llvm::cl::desc("Regex to match gpu.module names for XeVM target attach"),
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llvm::cl::init("")};
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PassOptions::Option<std::string> zebinTriple{
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*this, "zebin-triple", llvm::cl::desc("Target triple for XeVM codegen"),
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llvm::cl::init("spirv64-unknown-unknown")};
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PassOptions::Option<std::string> zebinChip{
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*this, "zebin-chip", llvm::cl::desc("Target chip (e.g. pvc, bmg)"),
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llvm::cl::init("bmg")};
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PassOptions::Option<unsigned> optLevel{
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*this, "opt-level",
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llvm::cl::desc("Optimization level for attached target/codegen"),
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llvm::cl::init(2)};
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PassOptions::Option<std::string> cmdOptions{
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*this, "igc-cmd-options",
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llvm::cl::desc("Additional downstream compiler command line options"),
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llvm::cl::init("")};
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// Options for MathExtendToSupportedTypes and ArithEmulateUnsupportedFloats,
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// run on the host/device module before conversion to LLVM to legalize math
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// and arith ops operating on floating-point types that the XeVM target
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// cannot handle natively (e.g. bf16).
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PassOptions::ListOption<std::string> unsupportedSourceTypes{
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*this, "unsupported-source-types",
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llvm::cl::desc("Floating-point source types without arithmetic/math "
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"support on the target (e.g. bf16)"),
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llvm::cl::list_init<std::string>(ArrayRef<std::string>{"bf16"})};
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PassOptions::Option<std::string> supportedTargetTypes{
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*this, "supported-target-types",
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llvm::cl::desc(
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"Floating-point target type used to emulate the unsupported "
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"source types via extf/truncf pairs"),
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llvm::cl::init("f32")};
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// Additional types (beyond the implicit f32/f64) that math ops are allowed
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// to run on directly. Maps to the `extra-types` option of
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// math-extend-to-supported-types. Leave empty to extend every non-f32/f64
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// math op to `supported-target-types`.
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PassOptions::ListOption<std::string> mathExtendExtraTypes{
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*this, "math-extend-extra-types",
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llvm::cl::desc(
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"Extra floating-point types with math op support on the target, "
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"in addition to f32 and f64 (maps to math-extend-to-supported-"
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"types `extra-types`)"),
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llvm::cl::list_init<std::string>(ArrayRef<std::string>{"f16"})};
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};
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//===----------------------------------------------------------------------===//
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// Building and Registering.
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//===----------------------------------------------------------------------===//
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/// Adds the GPU to NVVM pipeline to the given pass manager. Transforms main
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/// dialects into NVVM targets. Begins with GPU code regions, then handles host
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/// code.
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void buildLowerToNVVMPassPipeline(OpPassManager &pm,
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const GPUToNVVMPipelineOptions &options);
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/// Adds the GPU to ROCDL pipeline to the given pass manager. Transforms main
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/// dialects (arith, memref, scf, vector, gpu) into ROCDL/AMDGPU. Begins with
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/// GPU code regions, then handles host code.
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void buildLowerToROCDLPassPipeline(OpPassManager &pm,
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const GPUToROCDLPipelineOptions &options);
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/// Adds the GPU to XeVM pipeline to the given pass manager. Transforms main
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/// dialects into XeVM targets. Begins with GPU code regions, then handles host
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/// code.
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void buildLowerToXeVMPassPipeline(OpPassManager &pm,
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const GPUToXeVMPipelineOptions &options);
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/// Register all pipelines for the `gpu` dialect.
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void registerGPUToNVVMPipeline();
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void registerGPUToROCDLPipeline();
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void registerGPUToXeVMPipeline();
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} // namespace gpu
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} // namespace mlir
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#endif
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