1456 lines
60 KiB
C++
1456 lines
60 KiB
C++
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* AttrDef Declarations *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_ATTRDEF_CLASSES
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#undef GET_ATTRDEF_CLASSES
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namespace mlir {
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class AsmParser;
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class AsmPrinter;
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} // namespace mlir
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namespace mlir::NVVM {
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/// NVVM FPRoundingMode kind
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class FPRoundingModeAttr;
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/// Describes the saturation mode
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/// A `nvvm.sat_mode` attribute specifies the saturation mode for instructions
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/// involving floating points or integers. It can be one of the following
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/// values:
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/// - `none`: No saturation is applied.
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/// - `satfinite`: If the absolute value of input (ignoring sign) is greater
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/// than the `MAX_NORM` of the specified destination format, then the result
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/// is the sign-preserved `MAX_NORM` of the destination format and a positive
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/// `MAX_NORM` in unsigned datatypes for which the destination sign is not
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/// supported. If the input is `NaN`, then the result can be `NaN` or the
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/// `MAX_NORM` of the destination format, depending on the format.
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/// - `sat`: For integer destination types, this limits the value to `MININT..
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/// MAXINT` and applies to both signed and unsigned integer datatypes. For
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/// floating point destination types (applies to only `F16`, `F32`, and `F64`
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/// types), this limits the value to the range `[0.0, 1.0]` and flushes NaN
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/// results to positive zero.
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///
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt)
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class SaturationModeAttr;
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/// NVVM Cache Eviction Priority
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/// Enum cases:
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/// * evict_normal (`EvictNormal`)
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/// * evict_first (`EvictFirst`)
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/// * evict_last (`EvictLast`)
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/// * evict_unchanged (`EvictUnchanged`)
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/// * no_allocate (`NoAllocate`)
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class CacheEvictionPriorityAttr;
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/// NVVM Memory Space
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/// Enum cases:
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/// * generic (`Generic`)
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/// * global (`Global`)
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/// * shared (`Shared`)
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/// * constant (`Constant`)
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/// * local (`Local`)
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/// * tensor (`Tensor`)
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/// * shared_cluster (`SharedCluster`)
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class NVVMMemorySpaceAttr;
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/// NVVM Memory Scope kind
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class MemScopeKindAttr;
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/// Shared memory space
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class SharedSpaceAttr;
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/// NVVM Memory Ordering kind
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class MemOrderKindAttr;
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/// NVVM Reduction Kind attribute
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class ReductionKindAttr;
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/// NVVM barrier reduction operation
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class BarrierReductionAttr;
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/// Proxy kind
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/// ProxyKind attribute represents a memory proxy which is an abstract label
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/// applied to a method of memory access. When two memory operations use distinct
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/// methods of memory access, they are said to be different proxies.
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class ProxyKindAttr;
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/// NVVM set max register action
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class SetMaxRegisterActionAttr;
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/// NVVM shuffle kind
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class ShflKindAttr;
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/// NVVM vote sync kind
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class VoteSyncKindAttr;
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/// NVVM permute mode
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class PermuteModeAttr;
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/// NVVM load cache modifier kind
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/// Enum attribute of the different kinds of cache operators for load instructions.
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///
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#id62)
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class LoadCacheModifierKindAttr;
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/// MMA binary operations
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class MMAB1OpAttr;
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/// MMA overflow options
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class MMAIntOverflowAttr;
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/// MMA operation kind
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class MMAKindAttr;
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/// Attribute for MMA operation shape.
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class MMAShapeAttr;
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/// NVVM MMA layout
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class MMALayoutAttr;
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/// NVVM MMA types
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class MMATypesAttr;
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/// NVVM MMA frag type
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class MMAFragAttr;
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/// Matrix shape for ldmatrix and stmatrix
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class LdStMatrixShapeAttr;
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/// Element type for ldmatrix and stmatrix
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class LdStMatrixEltTypeAttr;
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/// MMA Scale Vector Sizes
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class ScaleVecSizeAttr;
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/// MMA Block Scale Format
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class BlockScaleFormatAttr;
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/// Block Scale Kind
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/// The MMABlockScaleKind attribute describes the allowed set of types for matrix A and B in the *.mma.{sp}.block_scale Op. The following are supported types for each kind:
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///
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/// ```
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/// +--------------+-------------------------------------------+
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/// | Matrix Kind | supported types for A / B |
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/// +--------------+-------------------------------------------+
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/// | mxf8f6f4 | e4m3, e5m2, e2m3, e3m2, e2m1 |
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/// | mxf4 | e2m1 |
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/// | mxf4nvf4 | e2m1 |
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/// +--------------+-------------------------------------------+
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/// ```
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class MMABlockScaleKindAttr;
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/// List of Load-Modes supported for TMA Tensor Ops
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/// TMA Tensor Ops support the following modes, when copying data from
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/// global memory to shared memory (i.e. load):
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///
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/// Tile Mode: It's the default mode. The source multi-dimensional tensor
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/// layout is preserved at the destination.
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-tiled-mode)
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///
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/// Im2col Mode: This mode is used when `im2colOffsets` operands are present.
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/// The elements in the Bounding Box of the source tensor are rearranged into
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/// columns at the destination. In this mode, the tensor has to be at least
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/// 3-dimensional. The number of `im2colOffsets` is `dims - 2` where `dims`
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/// is the dimension of the tensor.
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-im2col-mode)
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///
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/// Im2col_W Mode: This mode is similar to Im2Col mode with the restriction that
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/// elements are accessed across the W dimension only. The number of `im2colOffsets`
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/// are always two, referred as `wHalo` and `wOffset`.
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-im2col-w-w128-modes)
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///
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/// Im2col_W_128 Mode: This mode is similar to Im2Col_W mode with the number of
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/// elements accessed across the W dimension is always 128 only.
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-im2col-w-w128-modes)
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///
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/// Tile_Gather4 Mode: This mode is similar to Tile mode but works only on 2D tensor.
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/// In gather4 mode, four rows in the source 2D tensor are combined to form a single
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/// 2D tensor at the destination. This mode requires five co-ordinates. The first one
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/// represents the column-index followed by four row indices.
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/// [For more information, see PTX ISA](https://docs.nvidia.com/cuda/parallel-thread-execution/#tensor-tiled-scatter4-gather4-modes)
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class TMALoadModeAttr;
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/// NVVM TMA Store Mode
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class TMAStoreModeAttr;
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/// NVVM CTA group kind
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class CTAGroupKindAttr;
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/// NVVM Prefetch Cache Level
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/// Enum cases:
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/// * L1 (`L1`)
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/// * L2 (`L2`)
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class PrefetchCacheLevelAttr;
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/// NVVM TMA redux kind
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class TMAReduxKindAttr;
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/// WGMMA overflow options
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class WGMMAScaleInAttr;
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/// WGMMA input predicate
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class WGMMAScaleOutAttr;
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/// NVVM WGMMA types
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class WGMMATypesAttr;
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/// Action kind for grid dependency control
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/// Enum cases:
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/// * wait (`wait`)
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/// * launch_dependents (`launch_dependents`)
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class GridDepActionKindAttr;
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/// NVVM match sync kind
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class MatchSyncKindAttr;
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/// NVVM Tcgen05 fence kind
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class Tcgen05FenceKindAttr;
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/// NVVM Tcgen05 wait kind
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class Tcgen05WaitKindAttr;
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/// tcgen05 cp shapes
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class Tcgen05CpShapeAttr;
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/// tcgen05 cp multicast
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class Tcgen05CpMulticastAttr;
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/// tcgen05 cp source format
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class Tcgen05CpSrcFormatAttr;
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/// allowed 32-bit signless integer cases: 0, 1, 2, 3, 4
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class Tcgen05LdStShapeAttr;
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/// NVVM DotAccumulateType
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class DotAccumulateTypeAttr;
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/// NVVM ClusterLaunchControlQueryType
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/// Enum cases:
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/// * is_canceled (`IS_CANCELED`)
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/// * get_first_cta_id_x (`GET_FIRST_CTA_ID_X`)
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/// * get_first_cta_id_y (`GET_FIRST_CTA_ID_Y`)
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/// * get_first_cta_id_z (`GET_FIRST_CTA_ID_Z`)
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class ClusterLaunchControlQueryTypeAttr;
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/// tcgen05 MMA Supported Types
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/// The Tcgen05MMAKind attribute describes the allowed set of types for matrix A and B in the tcgen05.mma Ops.
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/// The following are supported types for each kind:
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///
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/// ```
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/// +-------------+--------------------------------------------+
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/// | Matrix Kind | supported types for A / B |
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/// +-------------+--------------------------------------------+
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/// | f16 | f16, bf16 |
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/// | tf32 | tf32 |
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/// | f8f6f4 | e4m3, e5m2, e2m3, e3m2, e2m1 |
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/// | i8 | unsigned 8b, signed 8b |
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/// | mxf8f6f4 | e4m3, e5m2, e2m3, e3m2, e2m1 |
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/// | mxf4 | e2m1 |
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/// | mxf4nvf4 | e2m1 |
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/// +-------------+--------------------------------------------+
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/// ```
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class Tcgen05MMAKindAttr;
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/// tcgen05.mma Collector Buffer Operation
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/// Tcgen05MMACollectorOp attribute specifies the collector buffer operations.
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/// The following are the supported operations:
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/// * discard : Release buffer after use (default)
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/// * lastuse : Mark buffer for last use
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/// * fill : Fill buffer
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/// * use : Use buffer without modification
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class Tcgen05MMACollectorOpAttr;
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/// tcgen05.mma block scale attribute
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class Tcgen05MMABlockScaleAttr;
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/// tcgen05 MMA Collector Buffer B Attribute
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class Tcgen05MMACollectorBBufferAttr;
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/// NVVM Tensormap Field Kind
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/// Enum cases:
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/// * global_address (`GLOBAL_ADDRESS`)
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/// * rank (`RANK`)
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/// * box_dim (`BOX_DIM`)
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/// * global_dim (`GLOBAL_DIM`)
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/// * global_stride (`GLOBAL_STRIDE`)
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/// * element_stride (`ELEMENT_STRIDE`)
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/// * elemtype (`ELEMTYPE`)
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/// * interleave_layout (`INTERLEAVE_LAYOUT`)
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/// * swizzle_mode (`SWIZZLE_MODE`)
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/// * swizzle_atomicity (`SWIZZLE_ATOMICITY`)
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/// * fill_mode (`FILL_MODE`)
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class TensormapFieldAttr;
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/// NVVM Tensormap Elemtype
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/// Enum cases:
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/// * u8 (`U8`)
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/// * u16 (`U16`)
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/// * u32 (`U32`)
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/// * s32 (`S32`)
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/// * u64 (`U64`)
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/// * s64 (`S64`)
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/// * f16 (`F16`)
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/// * f32 (`F32`)
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/// * f32.ftz (`F32_FTZ`)
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/// * f64 (`F64`)
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/// * bf16 (`BF16`)
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/// * tf32 (`TF32`)
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/// * tf32.ftz (`TF32_FTZ`)
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/// * b4x16 (`B4x16`)
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/// * b4x16_p64 (`B4x16P64`)
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/// * b6x16_p32 (`B6x16P32`)
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class TensormapElemtypeAttr;
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/// NVVM Tensormap Interleave Layout
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/// Enum cases:
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/// * no_interleave (`NO_INTERLEAVE`)
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/// * b16 (`B16`)
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/// * b32 (`B32`)
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class TensormapInterleaveLayoutAttr;
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/// NVVM Tensormap Swizzle Mode
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/// Enum cases:
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/// * no_swizzling (`NO_SWIZZLING`)
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/// * b32 (`B32`)
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/// * b64 (`B64`)
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/// * b128 (`B128`)
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/// * b96 (`B96`)
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class TensormapSwizzleModeAttr;
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/// NVVM Tensormap Swizzle Atomicity
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/// Enum cases:
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/// * b16 (`B16`)
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/// * b32 (`B32`)
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/// * b32_flip_b8 (`B32_FLIP_8B`)
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/// * b64 (`B64`)
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class TensormapSwizzleAtomicityAttr;
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/// NVVM Tensormap Fill Mode
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/// Enum cases:
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/// * zero (`ZERO`)
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/// * oob_nan (`OOB_NAN`)
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class TensormapFillModeAttr;
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/// GPU target attribute for controlling compilation of NVIDIA targets. All
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/// parameters decay into default values if not present.
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///
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/// Examples:
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///
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/// 1. Target with default values.
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/// ```
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/// gpu.module @mymodule [#nvvm.target] attributes {...} {
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/// ...
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/// }
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/// ```
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///
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/// 2. Target with `sm_90` chip and fast math.
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/// ```
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/// gpu.module @mymodule [#nvvm.target<chip = "sm_90", flags = {fast}>] {
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/// ...
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/// }
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/// ```
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class NVVMTargetAttr;
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namespace detail {
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struct FPRoundingModeAttrStorage;
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} // namespace detail
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class FPRoundingModeAttr : public ::mlir::Attribute::AttrBase<FPRoundingModeAttr, ::mlir::Attribute, detail::FPRoundingModeAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "nvvm.fp_rnd_mode";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static FPRoundingModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::FPRoundingMode value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"fp_rnd_mode"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::FPRoundingMode getValue() const;
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};
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namespace detail {
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struct SaturationModeAttrStorage;
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} // namespace detail
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class SaturationModeAttr : public ::mlir::Attribute::AttrBase<SaturationModeAttr, ::mlir::Attribute, detail::SaturationModeAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "nvvm.sat_mode";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static SaturationModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::SaturationMode value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"sat_mode"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::SaturationMode getValue() const;
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};
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namespace detail {
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struct CacheEvictionPriorityAttrStorage;
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} // namespace detail
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class CacheEvictionPriorityAttr : public ::mlir::Attribute::AttrBase<CacheEvictionPriorityAttr, ::mlir::Attribute, detail::CacheEvictionPriorityAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "nvvm.cache_eviction_priority";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static CacheEvictionPriorityAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::CacheEvictionPriority value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"cache_eviction_priority"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::CacheEvictionPriority getValue() const;
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};
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namespace detail {
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struct NVVMMemorySpaceAttrStorage;
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} // namespace detail
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class NVVMMemorySpaceAttr : public ::mlir::Attribute::AttrBase<NVVMMemorySpaceAttr, ::mlir::Attribute, detail::NVVMMemorySpaceAttrStorage, ::mlir::LLVM::LLVMAddrSpaceAttrInterface::Trait, ::mlir::ptr::MemorySpaceAttrInterface::Trait> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "nvvm.memory_space";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static NVVMMemorySpaceAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::NVVMMemorySpace value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"memory_space"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::NVVMMemorySpace getValue() const;
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unsigned getAddressSpace() const;
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bool isValidLoad(::mlir::Type type, ::mlir::ptr::AtomicOrdering ordering, std::optional<int64_t> alignment, const ::mlir::DataLayout *dataLayout, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError) const;
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bool isValidStore(::mlir::Type type, ::mlir::ptr::AtomicOrdering ordering, std::optional<int64_t> alignment, const ::mlir::DataLayout *dataLayout, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError) const;
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bool isValidAtomicOp(::mlir::ptr::AtomicBinOp op, ::mlir::Type type, ::mlir::ptr::AtomicOrdering ordering, std::optional<int64_t> alignment, const ::mlir::DataLayout *dataLayout, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError) const;
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bool isValidAtomicXchg(::mlir::Type type, ::mlir::ptr::AtomicOrdering successOrdering, ::mlir::ptr::AtomicOrdering failureOrdering, std::optional<int64_t> alignment, const ::mlir::DataLayout *dataLayout, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError) const;
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bool isValidAddrSpaceCast(::mlir::Type tgt, ::mlir::Type src, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError) const;
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bool isValidPtrIntCast(::mlir::Type intLikeTy, ::mlir::Type ptrLikeTy, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError) const;
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};
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namespace detail {
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struct MemScopeKindAttrStorage;
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} // namespace detail
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class MemScopeKindAttr : public ::mlir::Attribute::AttrBase<MemScopeKindAttr, ::mlir::Attribute, detail::MemScopeKindAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "nvvm.mem_scope";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static MemScopeKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MemScopeKind value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"mem_scope"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::MemScopeKind getValue() const;
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};
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namespace detail {
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struct SharedSpaceAttrStorage;
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} // namespace detail
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class SharedSpaceAttr : public ::mlir::Attribute::AttrBase<SharedSpaceAttr, ::mlir::Attribute, detail::SharedSpaceAttrStorage> {
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public:
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using Base::Base;
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static constexpr ::llvm::StringLiteral name = "nvvm.shared_space";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static SharedSpaceAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::SharedSpace value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"shared_space"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::SharedSpace getValue() const;
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};
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namespace detail {
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struct MemOrderKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MemOrderKindAttr : public ::mlir::Attribute::AttrBase<MemOrderKindAttr, ::mlir::Attribute, detail::MemOrderKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mem_order";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MemOrderKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MemOrderKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mem_order"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MemOrderKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct ReductionKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class ReductionKindAttr : public ::mlir::Attribute::AttrBase<ReductionKindAttr, ::mlir::Attribute, detail::ReductionKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.reduction_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static ReductionKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::ReductionKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"reduction_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::ReductionKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct BarrierReductionAttrStorage;
|
|
|
|
} // namespace detail
|
|
class BarrierReductionAttr : public ::mlir::Attribute::AttrBase<BarrierReductionAttr, ::mlir::Attribute, detail::BarrierReductionAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.reduction";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static BarrierReductionAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::BarrierReduction value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"reduction"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::BarrierReduction getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct ProxyKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class ProxyKindAttr : public ::mlir::Attribute::AttrBase<ProxyKindAttr, ::mlir::Attribute, detail::ProxyKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.proxy_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static ProxyKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::ProxyKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"proxy_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::ProxyKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct SetMaxRegisterActionAttrStorage;
|
|
|
|
} // namespace detail
|
|
class SetMaxRegisterActionAttr : public ::mlir::Attribute::AttrBase<SetMaxRegisterActionAttr, ::mlir::Attribute, detail::SetMaxRegisterActionAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.action";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static SetMaxRegisterActionAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::SetMaxRegisterAction value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"action"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::SetMaxRegisterAction getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct ShflKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class ShflKindAttr : public ::mlir::Attribute::AttrBase<ShflKindAttr, ::mlir::Attribute, detail::ShflKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.shfl_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static ShflKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::ShflKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"shfl_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::ShflKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct VoteSyncKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class VoteSyncKindAttr : public ::mlir::Attribute::AttrBase<VoteSyncKindAttr, ::mlir::Attribute, detail::VoteSyncKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.vote_sync_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static VoteSyncKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::VoteSyncKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"vote_sync_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::VoteSyncKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct PermuteModeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class PermuteModeAttr : public ::mlir::Attribute::AttrBase<PermuteModeAttr, ::mlir::Attribute, detail::PermuteModeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.permute_mode";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static PermuteModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::PermuteMode value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"permute_mode"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::PermuteMode getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct LoadCacheModifierKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class LoadCacheModifierKindAttr : public ::mlir::Attribute::AttrBase<LoadCacheModifierKindAttr, ::mlir::Attribute, detail::LoadCacheModifierKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.load_cache_modifier";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static LoadCacheModifierKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::LoadCacheModifierKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"load_cache_modifier"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::LoadCacheModifierKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMAB1OpAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMAB1OpAttr : public ::mlir::Attribute::AttrBase<MMAB1OpAttr, ::mlir::Attribute, detail::MMAB1OpAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mma_b1op";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMAB1OpAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMAB1Op value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mma_b1op"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMAB1Op getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMAIntOverflowAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMAIntOverflowAttr : public ::mlir::Attribute::AttrBase<MMAIntOverflowAttr, ::mlir::Attribute, detail::MMAIntOverflowAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mma_int_overflow";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMAIntOverflowAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMAIntOverflow value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mma_int_overflow"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMAIntOverflow getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMAKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMAKindAttr : public ::mlir::Attribute::AttrBase<MMAKindAttr, ::mlir::Attribute, detail::MMAKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mma_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMAKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMAKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mma_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMAKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMAShapeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMAShapeAttr : public ::mlir::Attribute::AttrBase<MMAShapeAttr, ::mlir::Attribute, detail::MMAShapeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.shape";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMAShapeAttr get(::mlir::MLIRContext *context, int m, int n, int k);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"shape"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
int getM() const;
|
|
int getN() const;
|
|
int getK() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMALayoutAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMALayoutAttr : public ::mlir::Attribute::AttrBase<MMALayoutAttr, ::mlir::Attribute, detail::MMALayoutAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mma_layout";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMALayoutAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMALayout value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mma_layout"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMALayout getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMATypesAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMATypesAttr : public ::mlir::Attribute::AttrBase<MMATypesAttr, ::mlir::Attribute, detail::MMATypesAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mma_type";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMATypesAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMATypes value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mma_type"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMATypes getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMAFragAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMAFragAttr : public ::mlir::Attribute::AttrBase<MMAFragAttr, ::mlir::Attribute, detail::MMAFragAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.mma_frag";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMAFragAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMAFrag value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"mma_frag"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMAFrag getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct LdStMatrixShapeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class LdStMatrixShapeAttr : public ::mlir::Attribute::AttrBase<LdStMatrixShapeAttr, ::mlir::Attribute, detail::LdStMatrixShapeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.ld_st_matrix_shape";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static LdStMatrixShapeAttr get(::mlir::MLIRContext *context, int m, int n);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"ld_st_matrix_shape"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
int getM() const;
|
|
int getN() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct LdStMatrixEltTypeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class LdStMatrixEltTypeAttr : public ::mlir::Attribute::AttrBase<LdStMatrixEltTypeAttr, ::mlir::Attribute, detail::LdStMatrixEltTypeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.ld_st_matrix_elt_type";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static LdStMatrixEltTypeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::LdStMatrixEltType value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"ld_st_matrix_elt_type"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::LdStMatrixEltType getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct ScaleVecSizeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class ScaleVecSizeAttr : public ::mlir::Attribute::AttrBase<ScaleVecSizeAttr, ::mlir::Attribute, detail::ScaleVecSizeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.scale_vec_size";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static ScaleVecSizeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::ScaleVecSize value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"scale_vec_size"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::ScaleVecSize getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct BlockScaleFormatAttrStorage;
|
|
|
|
} // namespace detail
|
|
class BlockScaleFormatAttr : public ::mlir::Attribute::AttrBase<BlockScaleFormatAttr, ::mlir::Attribute, detail::BlockScaleFormatAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.block_scale_format";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static BlockScaleFormatAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::BlockScaleFormat value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"block_scale_format"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::BlockScaleFormat getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MMABlockScaleKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MMABlockScaleKindAttr : public ::mlir::Attribute::AttrBase<MMABlockScaleKindAttr, ::mlir::Attribute, detail::MMABlockScaleKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.block_scale_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MMABlockScaleKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MMABlockScaleKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"block_scale_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MMABlockScaleKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct TMALoadModeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class TMALoadModeAttr : public ::mlir::Attribute::AttrBase<TMALoadModeAttr, ::mlir::Attribute, detail::TMALoadModeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tma_load_mode";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TMALoadModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TMALoadMode value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tma_load_mode"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TMALoadMode getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct TMAStoreModeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class TMAStoreModeAttr : public ::mlir::Attribute::AttrBase<TMAStoreModeAttr, ::mlir::Attribute, detail::TMAStoreModeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tma_store_mode";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TMAStoreModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TMAStoreMode value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tma_store_mode"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TMAStoreMode getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct CTAGroupKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class CTAGroupKindAttr : public ::mlir::Attribute::AttrBase<CTAGroupKindAttr, ::mlir::Attribute, detail::CTAGroupKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.cta_group";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static CTAGroupKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::CTAGroupKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"cta_group"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::CTAGroupKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct PrefetchCacheLevelAttrStorage;
|
|
|
|
} // namespace detail
|
|
class PrefetchCacheLevelAttr : public ::mlir::Attribute::AttrBase<PrefetchCacheLevelAttr, ::mlir::Attribute, detail::PrefetchCacheLevelAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.prefetch_cache_level";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static PrefetchCacheLevelAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::PrefetchCacheLevel value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"prefetch_cache_level"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::PrefetchCacheLevel getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct TMAReduxKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class TMAReduxKindAttr : public ::mlir::Attribute::AttrBase<TMAReduxKindAttr, ::mlir::Attribute, detail::TMAReduxKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tma_redux_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TMAReduxKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TMAReduxKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tma_redux_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TMAReduxKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct WGMMAScaleInAttrStorage;
|
|
|
|
} // namespace detail
|
|
class WGMMAScaleInAttr : public ::mlir::Attribute::AttrBase<WGMMAScaleInAttr, ::mlir::Attribute, detail::WGMMAScaleInAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.wgmma_scale_in";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static WGMMAScaleInAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::WGMMAScaleIn value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"wgmma_scale_in"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::WGMMAScaleIn getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct WGMMAScaleOutAttrStorage;
|
|
|
|
} // namespace detail
|
|
class WGMMAScaleOutAttr : public ::mlir::Attribute::AttrBase<WGMMAScaleOutAttr, ::mlir::Attribute, detail::WGMMAScaleOutAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.wgmma_scale_out";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static WGMMAScaleOutAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::WGMMAScaleOut value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"wgmma_scale_out"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::WGMMAScaleOut getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct WGMMATypesAttrStorage;
|
|
|
|
} // namespace detail
|
|
class WGMMATypesAttr : public ::mlir::Attribute::AttrBase<WGMMATypesAttr, ::mlir::Attribute, detail::WGMMATypesAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.wgmma_type";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static WGMMATypesAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::WGMMATypes value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"wgmma_type"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::WGMMATypes getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct GridDepActionKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class GridDepActionKindAttr : public ::mlir::Attribute::AttrBase<GridDepActionKindAttr, ::mlir::Attribute, detail::GridDepActionKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.grid_dep_action";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static GridDepActionKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::GridDepActionKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"grid_dep_action"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::GridDepActionKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct MatchSyncKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class MatchSyncKindAttr : public ::mlir::Attribute::AttrBase<MatchSyncKindAttr, ::mlir::Attribute, detail::MatchSyncKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.match_sync_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static MatchSyncKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::MatchSyncKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"match_sync_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::MatchSyncKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05FenceKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05FenceKindAttr : public ::mlir::Attribute::AttrBase<Tcgen05FenceKindAttr, ::mlir::Attribute, detail::Tcgen05FenceKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_fence";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05FenceKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05FenceKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_fence"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05FenceKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05WaitKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05WaitKindAttr : public ::mlir::Attribute::AttrBase<Tcgen05WaitKindAttr, ::mlir::Attribute, detail::Tcgen05WaitKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_wait";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05WaitKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05WaitKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_wait"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05WaitKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05CpShapeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05CpShapeAttr : public ::mlir::Attribute::AttrBase<Tcgen05CpShapeAttr, ::mlir::Attribute, detail::Tcgen05CpShapeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_cp_shape";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05CpShapeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05CpShape value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_cp_shape"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05CpShape getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05CpMulticastAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05CpMulticastAttr : public ::mlir::Attribute::AttrBase<Tcgen05CpMulticastAttr, ::mlir::Attribute, detail::Tcgen05CpMulticastAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_cp_multicast";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05CpMulticastAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05CpMulticast value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_cp_multicast"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05CpMulticast getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05CpSrcFormatAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05CpSrcFormatAttr : public ::mlir::Attribute::AttrBase<Tcgen05CpSrcFormatAttr, ::mlir::Attribute, detail::Tcgen05CpSrcFormatAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_cp_src_fmt";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05CpSrcFormatAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05CpSrcFormat value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_cp_src_fmt"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05CpSrcFormat getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05LdStShapeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05LdStShapeAttr : public ::mlir::Attribute::AttrBase<Tcgen05LdStShapeAttr, ::mlir::Attribute, detail::Tcgen05LdStShapeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_ldst_shape";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05LdStShapeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05LdStShape value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_ldst_shape"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05LdStShape getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct DotAccumulateTypeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class DotAccumulateTypeAttr : public ::mlir::Attribute::AttrBase<DotAccumulateTypeAttr, ::mlir::Attribute, detail::DotAccumulateTypeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.dot_accumulate_type";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static DotAccumulateTypeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::DotAccumulateType value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"dot_accumulate_type"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::DotAccumulateType getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct ClusterLaunchControlQueryTypeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class ClusterLaunchControlQueryTypeAttr : public ::mlir::Attribute::AttrBase<ClusterLaunchControlQueryTypeAttr, ::mlir::Attribute, detail::ClusterLaunchControlQueryTypeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.cluster_launch_control_query_type";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static ClusterLaunchControlQueryTypeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::ClusterLaunchControlQueryType value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"cluster_launch_control_query_type"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::ClusterLaunchControlQueryType getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05MMAKindAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05MMAKindAttr : public ::mlir::Attribute::AttrBase<Tcgen05MMAKindAttr, ::mlir::Attribute, detail::Tcgen05MMAKindAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_mma_kind";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05MMAKindAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05MMAKind value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_mma_kind"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05MMAKind getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05MMACollectorOpAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05MMACollectorOpAttr : public ::mlir::Attribute::AttrBase<Tcgen05MMACollectorOpAttr, ::mlir::Attribute, detail::Tcgen05MMACollectorOpAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_mma_collectorop";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05MMACollectorOpAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05MMACollectorOp value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_mma_collectorop"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05MMACollectorOp getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05MMABlockScaleAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05MMABlockScaleAttr : public ::mlir::Attribute::AttrBase<Tcgen05MMABlockScaleAttr, ::mlir::Attribute, detail::Tcgen05MMABlockScaleAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_mma_block_scale";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05MMABlockScaleAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05MMABlockScale value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_mma_block_scale"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05MMABlockScale getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct Tcgen05MMACollectorBBufferAttrStorage;
|
|
|
|
} // namespace detail
|
|
class Tcgen05MMACollectorBBufferAttr : public ::mlir::Attribute::AttrBase<Tcgen05MMACollectorBBufferAttr, ::mlir::Attribute, detail::Tcgen05MMACollectorBBufferAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tcgen05_mma_collectorb";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static Tcgen05MMACollectorBBufferAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::Tcgen05MMACollectorBBuffer value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tcgen05_mma_collectorb"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::Tcgen05MMACollectorBBuffer getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct TensormapFieldAttrStorage;
|
|
|
|
} // namespace detail
|
|
class TensormapFieldAttr : public ::mlir::Attribute::AttrBase<TensormapFieldAttr, ::mlir::Attribute, detail::TensormapFieldAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tensormap_field";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TensormapFieldAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TensormapField value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tensormap_field"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TensormapField getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct TensormapElemtypeAttrStorage;
|
|
|
|
} // namespace detail
|
|
class TensormapElemtypeAttr : public ::mlir::Attribute::AttrBase<TensormapElemtypeAttr, ::mlir::Attribute, detail::TensormapElemtypeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tensormap_elemtype";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TensormapElemtypeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TensormapElemtype value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tensormap_elemtype"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TensormapElemtype getValue() const;
|
|
};
|
|
namespace detail {
|
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struct TensormapInterleaveLayoutAttrStorage;
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} // namespace detail
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class TensormapInterleaveLayoutAttr : public ::mlir::Attribute::AttrBase<TensormapInterleaveLayoutAttr, ::mlir::Attribute, detail::TensormapInterleaveLayoutAttrStorage> {
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public:
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using Base::Base;
|
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static constexpr ::llvm::StringLiteral name = "nvvm.tensormap_interleave_layout";
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static TensormapInterleaveLayoutAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TensormapInterleaveLayout value);
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"tensormap_interleave_layout"};
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}
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
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::mlir::NVVM::TensormapInterleaveLayout getValue() const;
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};
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namespace detail {
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struct TensormapSwizzleModeAttrStorage;
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} // namespace detail
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class TensormapSwizzleModeAttr : public ::mlir::Attribute::AttrBase<TensormapSwizzleModeAttr, ::mlir::Attribute, detail::TensormapSwizzleModeAttrStorage> {
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public:
|
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using Base::Base;
|
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static constexpr ::llvm::StringLiteral name = "nvvm.tensormap_swizzle_mode";
|
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static constexpr ::llvm::StringLiteral dialectName = "nvvm";
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static TensormapSwizzleModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TensormapSwizzleMode value);
|
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static constexpr ::llvm::StringLiteral getMnemonic() {
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return {"tensormap_swizzle_mode"};
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|
}
|
|
|
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static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
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void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TensormapSwizzleMode getValue() const;
|
|
};
|
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namespace detail {
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|
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struct TensormapSwizzleAtomicityAttrStorage;
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} // namespace detail
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class TensormapSwizzleAtomicityAttr : public ::mlir::Attribute::AttrBase<TensormapSwizzleAtomicityAttr, ::mlir::Attribute, detail::TensormapSwizzleAtomicityAttrStorage> {
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public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tensormap_swizzle_atomicity";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TensormapSwizzleAtomicityAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TensormapSwizzleAtomicity value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tensormap_swizzle_atomicity"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TensormapSwizzleAtomicity getValue() const;
|
|
};
|
|
namespace detail {
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|
|
|
struct TensormapFillModeAttrStorage;
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|
|
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} // namespace detail
|
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class TensormapFillModeAttr : public ::mlir::Attribute::AttrBase<TensormapFillModeAttr, ::mlir::Attribute, detail::TensormapFillModeAttrStorage> {
|
|
public:
|
|
using Base::Base;
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.tensormap_fill_mode";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
static TensormapFillModeAttr get(::mlir::MLIRContext *context, ::mlir::NVVM::TensormapFillMode value);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"tensormap_fill_mode"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
::mlir::NVVM::TensormapFillMode getValue() const;
|
|
};
|
|
namespace detail {
|
|
|
|
struct NVVMTargetAttrStorage;
|
|
|
|
} // namespace detail
|
|
class NVVMTargetAttr : public ::mlir::Attribute::AttrBase<NVVMTargetAttr, ::mlir::Attribute, detail::NVVMTargetAttrStorage, ::mlir::gpu::TargetAttrVerifyInterface::Trait> {
|
|
public:
|
|
using Base::Base;
|
|
bool hasFlag(StringRef flag) const;
|
|
bool hasFastMath() const;
|
|
bool hasFtz() const;
|
|
bool hasCmdOptions() const;
|
|
std::optional<mlir::NamedAttribute> getCmdOptions() const;
|
|
LogicalResult verifyTarget(Operation *gpuModule);
|
|
static constexpr ::llvm::StringLiteral name = "nvvm.target";
|
|
static constexpr ::llvm::StringLiteral dialectName = "nvvm";
|
|
using Base::getChecked;
|
|
static NVVMTargetAttr get(::mlir::MLIRContext *context, int optLevel = 2, StringRef triple = "nvptx64-nvidia-cuda", StringRef chip = "sm_75", StringRef features = "", DictionaryAttr targetFlags = nullptr, ArrayAttr linkFiles = nullptr, bool verifyTarget = true);
|
|
static NVVMTargetAttr getChecked(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, ::mlir::MLIRContext *context, int optLevel = 2, StringRef triple = "nvptx64-nvidia-cuda", StringRef chip = "sm_75", StringRef features = "", DictionaryAttr targetFlags = nullptr, ArrayAttr linkFiles = nullptr, bool verifyTarget = true);
|
|
static ::llvm::LogicalResult verify(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, int O, ::llvm::StringRef triple, ::llvm::StringRef chip, ::llvm::StringRef features, DictionaryAttr flags, ArrayAttr link, bool verifyTarget);
|
|
static ::llvm::LogicalResult verifyInvariants(::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError, int O, ::llvm::StringRef triple, ::llvm::StringRef chip, ::llvm::StringRef features, DictionaryAttr flags, ArrayAttr link, bool verifyTarget);
|
|
static constexpr ::llvm::StringLiteral getMnemonic() {
|
|
return {"target"};
|
|
}
|
|
|
|
static ::mlir::Attribute parse(::mlir::AsmParser &odsParser, ::mlir::Type odsType);
|
|
void print(::mlir::AsmPrinter &odsPrinter) const;
|
|
int getO() const;
|
|
::llvm::StringRef getTriple() const;
|
|
::llvm::StringRef getChip() const;
|
|
::llvm::StringRef getFeatures() const;
|
|
DictionaryAttr getFlags() const;
|
|
ArrayAttr getLink() const;
|
|
bool getVerifyTarget() const;
|
|
::mlir::LogicalResult verifyTarget(::mlir::Operation *module) const;
|
|
};
|
|
|
|
} // namespace mlir::NVVM
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::FPRoundingModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::SaturationModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::CacheEvictionPriorityAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::NVVMMemorySpaceAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MemScopeKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::SharedSpaceAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MemOrderKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::ReductionKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::BarrierReductionAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::ProxyKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::SetMaxRegisterActionAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::ShflKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::VoteSyncKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::PermuteModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::LoadCacheModifierKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMAB1OpAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMAIntOverflowAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMAKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMAShapeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMALayoutAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMATypesAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMAFragAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::LdStMatrixShapeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::LdStMatrixEltTypeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::ScaleVecSizeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::BlockScaleFormatAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MMABlockScaleKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TMALoadModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TMAStoreModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::CTAGroupKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::PrefetchCacheLevelAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TMAReduxKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::WGMMAScaleInAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::WGMMAScaleOutAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::WGMMATypesAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::GridDepActionKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::MatchSyncKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05FenceKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05WaitKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05CpShapeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05CpMulticastAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05CpSrcFormatAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05LdStShapeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::DotAccumulateTypeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::ClusterLaunchControlQueryTypeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05MMAKindAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05MMACollectorOpAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05MMABlockScaleAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::Tcgen05MMACollectorBBufferAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TensormapFieldAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TensormapElemtypeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TensormapInterleaveLayoutAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TensormapSwizzleModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TensormapSwizzleAtomicityAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::TensormapFillModeAttr)
|
|
MLIR_DECLARE_EXPLICIT_TYPE_ID(::mlir::NVVM::NVVMTargetAttr)
|
|
|
|
#endif // GET_ATTRDEF_CLASSES
|
|
|