298 lines
12 KiB
TableGen
298 lines
12 KiB
TableGen
//===-- ROCDLEnums.td - ROCDL IR dialect enums ------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef ROCDLIR_ENUMS
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#define ROCDLIR_ENUMS
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include "mlir/IR/EnumAttr.td"
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//===----------------------------------------------------------------------===//
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// ROCDL enum definitions
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//===----------------------------------------------------------------------===//
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class ROCDL_I32Enum<string name, string summary, list<EnumCase> cases>
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: I32Enum<name, summary, cases> {
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let cppNamespace = "::mlir::ROCDL";
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}
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class ROCDL_I16BitEnum<string name, string summary,
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list<BitEnumCaseBase> cases>
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: I16BitEnum<name, summary, cases> {
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let cppNamespace = "::mlir::ROCDL";
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}
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class ROCDL_I32BitEnum<string name, string summary,
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list<BitEnumCaseBase> cases>
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: I32BitEnum<name, summary, cases> {
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let cppNamespace = "::mlir::ROCDL";
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}
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//===----------------------------------------------------------------------===//
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// Buffer out-of-bounds mode enum.
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//===----------------------------------------------------------------------===//
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// Keep these values in sync with OOBFlagValue in AMDGPUTargetMachine.cpp and
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// the LLVM IR verifier's AMDGPU module flag checks.
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def ROCDL_BufferOOBModeAny : I32EnumCase<"Any", 0, "any">;
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def ROCDL_BufferOOBModeRelaxed : I32EnumCase<"Relaxed", 1, "relaxed">;
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def ROCDL_BufferOOBModeStrict : I32EnumCase<"Strict", 2, "strict">;
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def ROCDL_BufferOOBMode :
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ROCDL_I32Enum<"BufferOOBMode", "ROCDL buffer out-of-bounds mode",
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[ROCDL_BufferOOBModeAny, ROCDL_BufferOOBModeRelaxed,
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ROCDL_BufferOOBModeStrict]>;
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def ROCDL_MFMAPermB : ROCDL_I32Enum<"MFMAPermB",
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"permutations of the lanes storing B in an MFMA",
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[
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I32EnumCase<"none", 0>,
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I32EnumCase<"bcast_first_32", 1>,
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I32EnumCase<"bcast_second_32", 2>,
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I32EnumCase<"rotate_16_right", 3>,
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I32EnumCase<"bcast_first_16", 4>,
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I32EnumCase<"bcast_second_16", 5>,
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I32EnumCase<"bcast_third_16", 6>,
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I32EnumCase<"bcast_fourth_16", 7>
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]>;
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def ROCDL_MFMANegModifierNone : I32BitEnumCaseNone<"none">;
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def ROCDL_MFMANegModifierA : I32BitEnumCaseBit<"neg_a", 0>;
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def ROCDL_MFMANegModifierB : I32BitEnumCaseBit<"neg_b", 1>;
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def ROCDL_MFMANegModifierC : I32BitEnumCaseBit<"neg_c", 2>;
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def ROCDL_MFMANegModifier : ROCDL_I32BitEnum<"MFMANegModifier",
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"negation modifier bitfield for gfx94x double-precision MFMA",
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[
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ROCDL_MFMANegModifierNone,
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ROCDL_MFMANegModifierA,
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ROCDL_MFMANegModifierB,
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ROCDL_MFMANegModifierC
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]> {
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let printBitEnumQuoted = 0;
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}
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def ROCDL_MatrixFormat : ROCDL_I32Enum<"MatrixFormat",
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"matrix operand formats selected by scaled MFMA/WMMA format fields",
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[
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I32EnumCase<"fp8_e4m3", 0>,
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I32EnumCase<"fp8_e5m2", 1>,
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I32EnumCase<"fp6_e2m3", 2>,
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I32EnumCase<"fp6_e3m2", 3>,
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I32EnumCase<"fp4_e2m1", 4>
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]>;
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def ROCDL_WMMAMatrixScale : ROCDL_I32Enum<"WMMAMatrixScale",
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"matrix scale row selector",
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[
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I32EnumCase<"row0", 0>,
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I32EnumCase<"row1", 1>
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]>;
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def ROCDL_WMMAMatrixScaleFormat : ROCDL_I32Enum<"WMMAMatrixScaleFormat",
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"matrix scale exponent formats",
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[
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I32EnumCase<"e8", 0>,
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I32EnumCase<"e5m3", 1>,
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I32EnumCase<"e4m3", 2>
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]>;
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def ROCDL_WMMACModifierNone : I16BitEnumCaseNone<"none">;
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def ROCDL_WMMACModifierNeg : I16BitEnumCaseBit<"neg", 0>;
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def ROCDL_WMMACModifierAbs : I16BitEnumCaseBit<"abs", 1>;
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def ROCDL_WMMACModifierNegAbs : BitEnumCaseGroup<"neg_abs",
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[ROCDL_WMMACModifierNeg, ROCDL_WMMACModifierAbs]>;
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def ROCDL_WMMACModifier : ROCDL_I16BitEnum<"WMMACModifier",
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"WMMA C operand modifiers",
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[
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ROCDL_WMMACModifierNone,
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ROCDL_WMMACModifierNeg,
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ROCDL_WMMACModifierAbs,
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ROCDL_WMMACModifierNegAbs
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]> {
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let printBitEnumPrimaryGroups = 1;
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let printBitEnumQuoted = 0;
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}
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def ROCDL_SchedGroupMaskNone : I32BitEnumCaseNone<"none">;
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def ROCDL_SchedGroupMaskNonMemNonSideEffect
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: I32BitEnumCaseBit<"non_mem_non_sideeffect", 0>;
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def ROCDL_SchedGroupMaskVALU : I32BitEnumCaseBit<"valu", 1>;
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def ROCDL_SchedGroupMaskSALU : I32BitEnumCaseBit<"salu", 2>;
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def ROCDL_SchedGroupMaskMFMAWMMA : I32BitEnumCaseBit<"mfma_wmma", 3>;
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def ROCDL_SchedGroupMaskAllVMEM : I32BitEnumCaseBit<"all_vmem", 4>;
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def ROCDL_SchedGroupMaskVMEMRead : I32BitEnumCaseBit<"vmem_read", 5>;
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def ROCDL_SchedGroupMaskVMEMWrite : I32BitEnumCaseBit<"vmem_write", 6>;
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def ROCDL_SchedGroupMaskAllDS : I32BitEnumCaseBit<"all_ds", 7>;
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def ROCDL_SchedGroupMaskDSRead : I32BitEnumCaseBit<"ds_read", 8>;
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def ROCDL_SchedGroupMaskDSWrite : I32BitEnumCaseBit<"ds_write", 9>;
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def ROCDL_SchedGroupMaskTranscendental
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: I32BitEnumCaseBit<"transcendental", 10>;
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def ROCDL_SchedGroupMaskLDSDMA : I32BitEnumCaseBit<"ldsdma", 11>;
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def ROCDL_SchedGroupMaskAll : BitEnumCaseGroup<"all",
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[ROCDL_SchedGroupMaskNonMemNonSideEffect, ROCDL_SchedGroupMaskVALU,
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ROCDL_SchedGroupMaskSALU, ROCDL_SchedGroupMaskMFMAWMMA,
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ROCDL_SchedGroupMaskAllVMEM, ROCDL_SchedGroupMaskVMEMRead,
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ROCDL_SchedGroupMaskVMEMWrite, ROCDL_SchedGroupMaskAllDS,
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ROCDL_SchedGroupMaskDSRead, ROCDL_SchedGroupMaskDSWrite,
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ROCDL_SchedGroupMaskTranscendental, ROCDL_SchedGroupMaskLDSDMA]>;
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def ROCDL_SchedGroupMask : ROCDL_I32BitEnum<"SchedGroupMask",
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"instruction type mask for scheduling barriers",
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[
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ROCDL_SchedGroupMaskNone,
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ROCDL_SchedGroupMaskNonMemNonSideEffect,
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ROCDL_SchedGroupMaskVALU,
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ROCDL_SchedGroupMaskSALU,
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ROCDL_SchedGroupMaskMFMAWMMA,
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ROCDL_SchedGroupMaskAllVMEM,
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ROCDL_SchedGroupMaskVMEMRead,
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ROCDL_SchedGroupMaskVMEMWrite,
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ROCDL_SchedGroupMaskAllDS,
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ROCDL_SchedGroupMaskDSRead,
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ROCDL_SchedGroupMaskDSWrite,
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ROCDL_SchedGroupMaskTranscendental,
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ROCDL_SchedGroupMaskLDSDMA,
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ROCDL_SchedGroupMaskAll
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]> {
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let printBitEnumPrimaryGroups = 1;
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let printBitEnumQuoted = 0;
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}
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def ROCDL_PreGfx12CachePolicyNone : I32BitEnumCaseNone<"none">;
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def ROCDL_PreGfx12CachePolicyGLC : I32BitEnumCaseBit<"glc", 0>;
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def ROCDL_PreGfx12CachePolicySLC : I32BitEnumCaseBit<"slc", 1>;
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def ROCDL_PreGfx12CachePolicyDLC : I32BitEnumCaseBit<"dlc", 2>;
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def ROCDL_PreGfx12CachePolicySWZ : I32BitEnumCaseBit<"swz", 3>;
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def ROCDL_PreGfx12CachePolicySCC : I32BitEnumCaseBit<"scc", 4>;
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def ROCDL_PreGfx12CachePolicyAll : BitEnumCaseGroup<"all",
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[ROCDL_PreGfx12CachePolicyGLC, ROCDL_PreGfx12CachePolicySLC,
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ROCDL_PreGfx12CachePolicyDLC, ROCDL_PreGfx12CachePolicySCC]>;
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def ROCDL_PreGfx12CachePolicyVolatile
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: I32BitEnumCaseBit<"volatile_op", 31, "volatile">;
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def ROCDL_PreGfx12CachePolicy : ROCDL_I32BitEnum<"PreGfx12CachePolicy",
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"pre-gfx12 buffer cache policy bits",
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[
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ROCDL_PreGfx12CachePolicyNone,
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ROCDL_PreGfx12CachePolicyGLC,
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ROCDL_PreGfx12CachePolicySLC,
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ROCDL_PreGfx12CachePolicyDLC,
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ROCDL_PreGfx12CachePolicySWZ,
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ROCDL_PreGfx12CachePolicySCC,
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ROCDL_PreGfx12CachePolicyAll,
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ROCDL_PreGfx12CachePolicyVolatile
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]> {
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let printBitEnumPrimaryGroups = 1;
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let printBitEnumQuoted = 0;
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}
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def ROCDL_Gfx942CachePolicyNone : I32BitEnumCaseNone<"none">;
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def ROCDL_Gfx942CachePolicySC0 : I32BitEnumCaseBit<"sc0", 0>;
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def ROCDL_Gfx942CachePolicyNT : I32BitEnumCaseBit<"nt", 1>;
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def ROCDL_Gfx942CachePolicySWZ : I32BitEnumCaseBit<"swz", 3>;
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def ROCDL_Gfx942CachePolicySC1 : I32BitEnumCaseBit<"sc1", 4>;
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def ROCDL_Gfx942CachePolicyVolatile
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: I32BitEnumCaseBit<"volatile_op", 31, "volatile">;
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def ROCDL_Gfx942CachePolicy : ROCDL_I32BitEnum<"Gfx942CachePolicy",
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"gfx942 buffer cache policy bits",
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[
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ROCDL_Gfx942CachePolicyNone,
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ROCDL_Gfx942CachePolicySC0,
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ROCDL_Gfx942CachePolicyNT,
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ROCDL_Gfx942CachePolicySWZ,
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ROCDL_Gfx942CachePolicySC1,
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ROCDL_Gfx942CachePolicyVolatile
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]> {
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let printBitEnumQuoted = 0;
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}
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def ROCDL_Gfx12CachePolicyNone : I32BitEnumCaseNone<"none">;
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def ROCDL_Gfx12CachePolicyNT : I32BitEnumCaseBit<"nt", 0>;
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def ROCDL_Gfx12CachePolicyHT : I32BitEnumCaseBit<"ht", 1>;
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// Helper bit for temporal encodings. Keep this out of the enum case list: if
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// listed there, the generated printer may print this bit directly instead of
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// using the named nt_rt/rt_nt/nt_ht/nt_wb groups below.
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def ROCDL_Gfx12CachePolicyTemporalBit2 : I32BitEnumCaseBit<"temporal_bit2", 2>;
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def ROCDL_Gfx12CachePolicyLU : BitEnumCaseGroup<"lu",
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[ROCDL_Gfx12CachePolicyNT, ROCDL_Gfx12CachePolicyHT]>;
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def ROCDL_Gfx12CachePolicyNTRT : BitEnumCaseGroup<"nt_rt",
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[ROCDL_Gfx12CachePolicyTemporalBit2]>;
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def ROCDL_Gfx12CachePolicyRTNT : BitEnumCaseGroup<"rt_nt",
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[ROCDL_Gfx12CachePolicyNT, ROCDL_Gfx12CachePolicyTemporalBit2]>;
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def ROCDL_Gfx12CachePolicyNTHT : BitEnumCaseGroup<"nt_ht",
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[ROCDL_Gfx12CachePolicyHT, ROCDL_Gfx12CachePolicyTemporalBit2]>;
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def ROCDL_Gfx12CachePolicyNTWB : BitEnumCaseGroup<"nt_wb",
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[ROCDL_Gfx12CachePolicyNT, ROCDL_Gfx12CachePolicyHT,
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ROCDL_Gfx12CachePolicyTemporalBit2]>;
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def ROCDL_Gfx12CachePolicyScopeSE : I32BitEnumCaseBit<"scope_se", 3>;
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def ROCDL_Gfx12CachePolicyScopeDev : I32BitEnumCaseBit<"scope_dev", 4>;
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def ROCDL_Gfx12CachePolicyScopeSys : BitEnumCaseGroup<"scope_sys",
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[ROCDL_Gfx12CachePolicyScopeSE, ROCDL_Gfx12CachePolicyScopeDev]>;
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def ROCDL_Gfx12CachePolicyNV : I32BitEnumCaseBit<"nv", 5>;
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def ROCDL_Gfx12CachePolicySWZ : I32BitEnumCaseBit<"swz", 6>;
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def ROCDL_Gfx12CachePolicySCAL : I32BitEnumCaseBit<"scal", 11>;
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def ROCDL_Gfx12CachePolicyVolatile
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: I32BitEnumCaseBit<"volatile_op", 31, "volatile">;
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def ROCDL_Gfx12CachePolicy : ROCDL_I32BitEnum<"Gfx12CachePolicy",
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"gfx12 cache policy bits",
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[
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ROCDL_Gfx12CachePolicyNone,
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ROCDL_Gfx12CachePolicyNT,
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ROCDL_Gfx12CachePolicyHT,
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ROCDL_Gfx12CachePolicyLU,
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ROCDL_Gfx12CachePolicyNTRT,
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ROCDL_Gfx12CachePolicyRTNT,
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ROCDL_Gfx12CachePolicyNTHT,
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ROCDL_Gfx12CachePolicyNTWB,
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ROCDL_Gfx12CachePolicyScopeSE,
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ROCDL_Gfx12CachePolicyScopeDev,
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ROCDL_Gfx12CachePolicyScopeSys,
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ROCDL_Gfx12CachePolicyNV,
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ROCDL_Gfx12CachePolicySWZ,
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ROCDL_Gfx12CachePolicySCAL,
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ROCDL_Gfx12CachePolicyVolatile
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]> {
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let printBitEnumPrimaryGroups = 1;
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let printBitEnumQuoted = 0;
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}
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def ROCDL_Gfx12AtomicCachePolicyNone : I32BitEnumCaseNone<"none">;
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// Note: this bit **will** be set automatically by the backend, you do
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// **not** need to include it in the policy, it's included for readability.
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def ROCDL_Gfx12AtomicCachePolicyReturn
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: I32BitEnumCaseBit<"keep_return", 0, "return">;
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def ROCDL_Gfx12AtomicCachePolicyNT : I32BitEnumCaseBit<"nt", 1>;
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def ROCDL_Gfx12AtomicCachePolicyCascade
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: I32BitEnumCaseBit<"cascade", 2>;
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def ROCDL_Gfx12AtomicCachePolicyScopeSE
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: I32BitEnumCaseBit<"scope_se", 3>;
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def ROCDL_Gfx12AtomicCachePolicyScopeDev
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: I32BitEnumCaseBit<"scope_dev", 4>;
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def ROCDL_Gfx12AtomicCachePolicyScopeSys
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: BitEnumCaseGroup<"scope_sys",
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[ROCDL_Gfx12AtomicCachePolicyScopeSE,
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ROCDL_Gfx12AtomicCachePolicyScopeDev]>;
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def ROCDL_Gfx12AtomicCachePolicyNV : I32BitEnumCaseBit<"nv", 5>;
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def ROCDL_Gfx12AtomicCachePolicyVolatile
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: I32BitEnumCaseBit<"volatile_op", 31, "volatile">;
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def ROCDL_Gfx12AtomicCachePolicy : ROCDL_I32BitEnum<"Gfx12AtomicCachePolicy",
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"gfx12 atomic cache policy bits",
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[
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ROCDL_Gfx12AtomicCachePolicyNone,
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ROCDL_Gfx12AtomicCachePolicyReturn,
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ROCDL_Gfx12AtomicCachePolicyNT,
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ROCDL_Gfx12AtomicCachePolicyCascade,
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ROCDL_Gfx12AtomicCachePolicyScopeSE,
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ROCDL_Gfx12AtomicCachePolicyScopeDev,
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ROCDL_Gfx12AtomicCachePolicyScopeSys,
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ROCDL_Gfx12AtomicCachePolicyNV,
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ROCDL_Gfx12AtomicCachePolicyVolatile
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]> {
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let printBitEnumPrimaryGroups = 1;
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let printBitEnumQuoted = 0;
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}
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#endif // ROCDLIR_ENUMS
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