122 lines
5.5 KiB
TableGen
122 lines
5.5 KiB
TableGen
//===-- NVGPU.td - Attribute defs for NVGPU dialect *- tablegen -*---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_DIALECT_NVGPU_IR_NVGPU_TD
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#define MLIR_DIALECT_NVGPU_IR_NVGPU_TD
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include "mlir/Dialect/LLVMIR/NVVMDialect.td"
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include "mlir/Interfaces/InferTypeOpInterface.td"
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include "mlir/Interfaces/SideEffectInterfaces.td"
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include "mlir/IR/AttrTypeBase.td"
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include "mlir/IR/OpBase.td"
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include "mlir/IR/EnumAttr.td"
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def NVGPU_Dialect : Dialect {
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let name = "nvgpu";
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let cppNamespace = "::mlir::nvgpu";
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let dependentDialects = ["NVVM::NVVMDialect"];
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let description = [{
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The `NVGPU` dialect provides a bridge between higher-level target-agnostic
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dialects (GPU and Vector) and the lower-level target-specific dialect
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(LLVM IR based NVVM dialect) for NVIDIA GPUs. This allow representing PTX
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specific operations while using MLIR high level dialects such as Memref
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and Vector for memory and target-specific register operands, respectively.
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}];
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let useDefaultTypePrinterParser = 1;
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let useDefaultAttributePrinterParser = 1;
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let extraClassDeclaration = [{
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/// Return true if the given MemRefType has an integer address
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/// space that matches the NVVM shared memory address space or
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/// is a gpu::AddressSpaceAttr attribute with value 'workgroup`.
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static bool hasSharedMemoryAddressSpace(MemRefType type);
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/// Return true if the given Attribute has an integer address
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/// space that matches the NVVM shared memory address space or
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/// is a gpu::AddressSpaceAttr attribute with value 'workgroup`.
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static bool isSharedMemoryAddressSpace(Attribute type);
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/// Defines the MemRef memory space attribute numeric value that indicates
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/// a memref is located in global memory. This should correspond to the
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/// value used in NVVM.
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static constexpr unsigned kGlobaldMemoryAddressSpace = 1;
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/// Defines the MemRef memory space attribute numeric value that indicates
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/// a memref is located in shared memory. This should correspond to the
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/// value used in NVVM.
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static constexpr unsigned kSharedMemoryAddressSpace = 3;
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}];
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}
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//===----------------------------------------------------------------------===//
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// NVGPU Attribute Definitions
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//===----------------------------------------------------------------------===//
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def TensorMapSwizzleNone : I32EnumAttrCase<"SWIZZLE_NONE", 0, "none">;
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def TensorMapSwizzle32B : I32EnumAttrCase<"SWIZZLE_32B", 1, "swizzle_32b">;
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def TensorMapSwizzle64B : I32EnumAttrCase<"SWIZZLE_64B", 2, "swizzle_64b">;
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def TensorMapSwizzle128B : I32EnumAttrCase<"SWIZZLE_128B", 3, "swizzle_128b">;
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def TensorMapSwizzleKind : I32EnumAttr<"TensorMapSwizzleKind",
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"Tensor map swizzling mode of shared memory banks",
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[ TensorMapSwizzleNone, TensorMapSwizzle32B, TensorMapSwizzle64B,
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TensorMapSwizzle128B]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::nvgpu";
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}
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def TensorMapL2PromoNone : I32EnumAttrCase<"L2PROMO_NONE", 0, "none">;
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def TensorMapL2Promo64B : I32EnumAttrCase<"L2PROMO_64B", 1, "l2promo_64b">;
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def TensorMapL2Promo128B : I32EnumAttrCase<"L2PROMO_128B", 2, "l2promo_128b">;
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def TensorMapL2Promo256B : I32EnumAttrCase<"L2PROMO_256B", 3, "l2promo_256b">;
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def TensorMapL2PromoKind : I32EnumAttr<"TensorMapL2PromoKind",
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"Tensor map L2 promotion type",
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[ TensorMapL2PromoNone, TensorMapL2Promo64B, TensorMapL2Promo128B,
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TensorMapL2Promo256B]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::nvgpu";
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}
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def TensorMapOOBZero : I32EnumAttrCase<"OOB_ZERO", 0, "zero">;
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def TensorMapOOBNaN : I32EnumAttrCase<"OOB_NAN", 1, "nan">;
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def TensorMapOOBKind : I32EnumAttr<"TensorMapOOBKind",
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"Tensor map out-of-bounds fill type",
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[ TensorMapOOBZero, TensorMapOOBNaN]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::nvgpu";
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}
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def TensorMapInterleaveNone : I32EnumAttrCase<"INTERLEAVE_NONE", 0, "none">;
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def TensorMapInterleave16B : I32EnumAttrCase<"INTERLEAVE_16B", 1, "interleave_16b">;
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def TensorMapInterleave32B : I32EnumAttrCase<"INTERLEAVE_32B", 2, "interleave_32b">;
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def TensorMapInterleaveKind : I32EnumAttr<"TensorMapInterleaveKind",
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"Tensor map interleave layout type",
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[ TensorMapInterleaveNone, TensorMapInterleave16B, TensorMapInterleave32B]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::nvgpu";
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}
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def RcpApprox : I32EnumAttrCase<"APPROX", 0, "approx">;
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def RcpRN : I32EnumAttrCase<"RN", 1, "rn">;
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def RcpRZ : I32EnumAttrCase<"RZ", 2, "rz">;
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def RcpRM : I32EnumAttrCase<"RM", 3, "rm">;
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def RcpRP : I32EnumAttrCase<"RP", 4, "rp">;
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def RcpRoundingMode : I32EnumAttr<"RcpRoundingMode", "Rounding mode of rcp",
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[RcpApprox, RcpRN, RcpRZ, RcpRM, RcpRP]> {
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let genSpecializedAttr = 0;
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let cppNamespace = "::mlir::nvgpu";
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}
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def TensorMapSwizzleAttr : EnumAttr<NVGPU_Dialect, TensorMapSwizzleKind, "swizzle">;
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def TensorMapL2PromoAttr : EnumAttr<NVGPU_Dialect, TensorMapL2PromoKind, "l2promo">;
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def TensorMapOOBAttr : EnumAttr<NVGPU_Dialect, TensorMapOOBKind, "oob">;
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def TensorMapInterleaveAttr : EnumAttr<NVGPU_Dialect, TensorMapInterleaveKind, "interleave">;
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def RcpRoundingModeAttr : EnumAttr<NVGPU_Dialect, RcpRoundingMode, "rcp_rounding_mode">;
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#endif // MLIR_DIALECT_NVGPU_IR_NVGPU_TD
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