3680 lines
366 KiB
Plaintext
3680 lines
366 KiB
Plaintext
make -C targets/fpga/genesys2 bitstream
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make[1]: Entering directory '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2'
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make[2]: Entering directory '/home/onur/Desktop/tmp/rocket-chip/soc/software'
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make[3]: Entering directory '/home/onur/Desktop/tmp/rocket-chip/soc/software/bootloader'
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DAPP_FLASH_OFFSET=0x01800000UL -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c start.S -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/start.S.o
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DAPP_FLASH_OFFSET=0x01800000UL -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c main.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/main.c.o
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DAPP_FLASH_OFFSET=0x01800000UL -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/init.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bsp_init.c.o
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DAPP_FLASH_OFFSET=0x01800000UL -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/uart.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bsp_uart.c.o
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DAPP_FLASH_OFFSET=0x01800000UL -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/spi_flash.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bsp_spi_flash.c.o
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DAPP_FLASH_OFFSET=0x01800000UL -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/start.S.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/main.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bsp_init.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bsp_uart.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bsp_spi_flash.c.o -T linker.ld -nostdlib -static -Wl,--gc-sections -Wl,--defsym=__dtim_base=0x80000000 -Wl,--defsym=__dtim_size=0x00100000 -Wl,-Map,/home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.map -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.elf
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-objcopy -O binary /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.elf /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.img
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-objdump -d -S /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.elf > /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.dump
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-size /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.elf
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text data bss dec hex filename
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1569 0 0 1569 621 /home/onur/Desktop/tmp/rocket-chip/soc/out/software/bootloader/bootloader.elf
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make[3]: Leaving directory '/home/onur/Desktop/tmp/rocket-chip/soc/software/bootloader'
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make[3]: Entering directory '/home/onur/Desktop/tmp/rocket-chip/soc/software/hello_uart'
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../common/start.S -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/common_start.S.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../common/syscalls.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/common_syscalls.c.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/init.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_init.c.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/uart.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_uart.c.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/plic.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_plic.c.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/irq.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_irq.c.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c ../bsp/drivers/spi_flash.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_spi_flash.c.o
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mkdir -p /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL -c main.c -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/main.c.o
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-gcc -march=rv64imafdc_zicsr_zifencei -mabi=lp64d -mcmodel=medany -Os -ffreestanding -fno-builtin -fno-common -Wall -Wextra -I../bsp/include -DBSP_UART_CLOCK_HZ=50000000UL -DBSP_UART_BAUDRATE=115200UL -DBSP_DTIM_BASE=0x80000000UL -DBSP_DTIM_SIZE=0x00100000UL /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/common_start.S.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/common_syscalls.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_init.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_uart.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_plic.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_irq.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/bsp_spi_flash.c.o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/main.c.o -T ../common/linker_ram.ld -nostartfiles -static -Wl,--gc-sections -Wl,--defsym=__dtim_base=0x80000000 -Wl,--defsym=__dtim_size=0x00100000 -Wl,-Map,/home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.map -Wl,--start-group -lc -lgcc -Wl,--end-group -o /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf
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/tools/toolchains/rvtc-medany/riscv64-unknown-elf/bin/ld: warning: /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf has a LOAD segment with RWX permissions
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-objcopy -O binary /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.img
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-objdump -d -S /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf > /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.dump
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/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-size /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf
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text data bss dec hex filename
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38000 2880 656 41536 a240 /home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf
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make[3]: Leaving directory '/home/onur/Desktop/tmp/rocket-chip/soc/software/hello_uart'
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python3 "/home/onur/Desktop/tmp/rocket-chip/soc/software/tools/make_flash_image.py" \
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--elf "/home/onur/Desktop/tmp/rocket-chip/soc/out/software/hello_uart/hello_uart.elf" \
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--out "/home/onur/Desktop/tmp/rocket-chip/soc/out/flash/hello_uart.flash.bin" \
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--flash-offset "0x01800000" \
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--objcopy "/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-objcopy" \
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--readelf "/tools/toolchains/rvtc-medany/bin/riscv64-unknown-elf-readelf"
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image: /home/onur/Desktop/tmp/rocket-chip/soc/out/flash/hello_uart.flash.bin
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flash_offset: 0x01800000
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payload_flash_offset: 0x01800040
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load_addr: 0x80000000
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entry: 0x80000000
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size: 40880
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crc32: 0xb277dc93
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make[2]: Leaving directory '/home/onur/Desktop/tmp/rocket-chip/soc/software'
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[info] compiling 7 Scala sources to /home/onur/Desktop/tmp/rocket-chip/out/mill-build/compile.dest/classes ...
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[warn] /home/onur/Desktop/tmp/rocket-chip/dependencies/chisel/build.sc:250:38: Auto-application to `()` is deprecated. Supply the empty argument list `()` explicitly to invoke method ctx,
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[warn] or remove the empty argument list from its definition (Java-defined methods are exempt).
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[warn] In Scala 3, an unapplied method like this will be eta-expanded into a function.
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[warn] def circtInstallPath = T(os.Path(T.ctx.env.get("CIRCT_INSTALL_PATH").getOrElse("/usr/local")))
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[warn] ^
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[warn] /home/onur/Desktop/tmp/rocket-chip/dependencies/chisel/build.sc:117:56: method lineStream in trait ProcessBuilder is deprecated (since 2.13.0): use lazyLines
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[warn] val lines = Process(Seq("firtool", "--version")).lineStream
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[warn] ^
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[warn] /home/onur/Desktop/tmp/rocket-chip/build.sc:287:155: method any2stringadd in object Predef is deprecated (since 2.13.0): Implicit injection of + is deprecated. Convert to String to call +
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[warn] |"$${CMAKE_CXX_FLAGS} -DVERILATOR -DTEST_HARNESS=VTestHarness -include VTestHarness.h -include verilator.h -include ${generator.elaborate().path / config + ".plusArgs"}")
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[warn] ^
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[warn] three warnings found
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[info] done compiling
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Compiling compiler interface...
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[info] compiling 1 Scala source to /home/onur/Desktop/tmp/rocket-chip/out/macros/compile.dest/classes ...
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[info] done compiling
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[info] compiling 7 Scala sources to /home/onur/Desktop/tmp/rocket-chip/out/foreign-modules/dependencies/chisel/build/plugin/2.13.12/compile.dest/classes ...
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[info] done compiling
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[info] compiling 20 Scala sources to /home/onur/Desktop/tmp/rocket-chip/out/hardfloat/6.7.0/compile.dest/classes ...
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[warn] 535 feature warnings; re-run with -feature for details
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[warn] one warning found
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[info] done compiling
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[info] compiling 1 Scala source to /home/onur/Desktop/tmp/rocket-chip/out/cde/compile.dest/classes ...
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[info] done compiling
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[info] compiling 36 Scala sources to /home/onur/Desktop/tmp/rocket-chip/out/diplomacy/6.7.0/compile.dest/classes ...
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[warn] /home/onur/Desktop/tmp/rocket-chip/dependencies/diplomacy/diplomacy/src/diplomacy/nodes/NodeImp.scala:63:20: parameter node in method mixI is never used
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[warn] def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu
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[warn] ^
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[warn] /home/onur/Desktop/tmp/rocket-chip/dependencies/diplomacy/diplomacy/src/diplomacy/nodes/NodeImp.scala:138:20: parameter node in method mixO is never used
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[warn] def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd
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[warn] ^
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[warn] two warnings found
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[info] done compiling
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[info] compiling 323 Scala sources to /home/onur/Desktop/tmp/rocket-chip/out/rocketchip/6.7.0/compile.dest/classes ...
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[warn] 3 deprecations
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[warn] 1 deprecation (since 6.6.0)
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[warn] 1 deprecation (since rocket-chip 1.2)
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[warn] 5 deprecations in total; re-run with -deprecation for details
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[warn] 2937 feature warnings; re-run with -feature for details
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[warn] 5 warnings found
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[info] done compiling
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Interrupt map (1 harts 10 interrupts):
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[1, 1] => dev
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[2, 2] => dev
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[3, 3] => dev
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[4, 4] => dev
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[5, 5] => dev
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[6, 6] => dev
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[7, 7] => dev
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[8, 8] => dev
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[9, 9] => dev
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[10, 10] => dev
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-dev";
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model = "freechips,rocketchip-unknown";
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L27: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <1000000>;
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L6: cpu@0 {
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clock-frequency = <0>;
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compatible = "sifive,rocket0", "riscv";
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device_type = "cpu";
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hardware-exec-breakpoint-count = <1>;
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i-cache-block-size = <64>;
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i-cache-sets = <64>;
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i-cache-size = <4096>;
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reg = <0x0>;
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riscv,isa = "rv64imafdczicsr_zifencei_zihpm_xrocket";
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riscv,pmpgranularity = <4>;
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riscv,pmpregions = <8>;
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sifive,dtim = <&L5>;
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status = "okay";
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timebase-frequency = <1000000>;
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L3: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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L26: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
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ranges;
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L1: cbus_clock {
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "cbus_clock";
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compatible = "fixed-clock";
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};
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L7: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&L3 3 &L3 7>;
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reg = <0x2000000 0x10000>;
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reg-names = "control";
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};
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L9: debug-controller@0 {
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compatible = "sifive,debug-013", "riscv,debug-013";
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debug-attach = "dmi";
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interrupts-extended = <&L3 65535>;
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reg = <0x0 0x1000>;
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reg-names = "control";
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};
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L5: dtim@80000000 {
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compatible = "sifive,dtim0";
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reg = <0x80000000 0x100000>;
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reg-names = "mem";
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};
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L2: error-device@3000 {
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compatible = "sifive,error0";
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reg = <0x3000 0x1000>;
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};
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L15: gps-acq@10020000 {
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compatible = "anka,gps-acq-apb";
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interrupt-parent = <&L8>;
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interrupts = <1>;
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reg = <0x10020000 0x1000>;
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};
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L16: gps-tracking0@10021000 {
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compatible = "anka,gps-tracking-apb";
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interrupt-parent = <&L8>;
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interrupts = <2>;
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reg = <0x10021000 0x1000>;
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};
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L17: gps-tracking1@10022000 {
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compatible = "anka,gps-tracking-apb";
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interrupt-parent = <&L8>;
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interrupts = <3>;
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reg = <0x10022000 0x1000>;
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};
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L18: gps-tracking2@10023000 {
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|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <4>;
|
|
reg = <0x10023000 0x1000>;
|
|
};
|
|
L19: gps-tracking3@10024000 {
|
|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <5>;
|
|
reg = <0x10024000 0x1000>;
|
|
};
|
|
L20: gps-tracking4@10025000 {
|
|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <6>;
|
|
reg = <0x10025000 0x1000>;
|
|
};
|
|
L21: gps-tracking5@10026000 {
|
|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <7>;
|
|
reg = <0x10026000 0x1000>;
|
|
};
|
|
L22: gps-tracking6@10027000 {
|
|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <8>;
|
|
reg = <0x10027000 0x1000>;
|
|
};
|
|
L23: gps-tracking7@10028000 {
|
|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <9>;
|
|
reg = <0x10028000 0x1000>;
|
|
};
|
|
L24: gps-tracking8@10029000 {
|
|
compatible = "anka,gps-tracking-apb";
|
|
interrupt-parent = <&L8>;
|
|
interrupts = <10>;
|
|
reg = <0x10029000 0x1000>;
|
|
};
|
|
L8: interrupt-controller@c000000 {
|
|
#interrupt-cells = <1>;
|
|
compatible = "riscv,plic0";
|
|
interrupt-controller;
|
|
interrupts-extended = <&L3 11>;
|
|
reg = <0xc000000 0x4000000>;
|
|
reg-names = "control";
|
|
riscv,max-priority = <7>;
|
|
riscv,ndev = <10>;
|
|
};
|
|
L0: pbus_clock {
|
|
#clock-cells = <0>;
|
|
clock-frequency = <100000000>;
|
|
clock-output-names = "pbus_clock";
|
|
compatible = "fixed-clock";
|
|
};
|
|
L12: rom@10000 {
|
|
compatible = "sifive,rom0";
|
|
reg = <0x10000 0x10000>;
|
|
reg-names = "mem";
|
|
};
|
|
L14: spi@10014000 {
|
|
compatible = "rocket,fpga-spi";
|
|
reg = <0x10014000 0x1000>;
|
|
reg-names = "control";
|
|
};
|
|
L13: uart@10013000 {
|
|
compatible = "rocket,fpga-uart";
|
|
reg = <0x10013000 0x1000>;
|
|
reg-names = "control";
|
|
};
|
|
};
|
|
};
|
|
|
|
Generated Address Map
|
|
0 - 1000 ARWX debug-controller@0
|
|
3000 - 4000 ARWX error-device@3000
|
|
10000 - 20000 R X rom@10000
|
|
2000000 - 2010000 ARW clint@2000000
|
|
c000000 - 10000000 ARW interrupt-controller@c000000
|
|
10013000 - 10014000 ARW uart@10013000
|
|
10014000 - 10015000 ARW spi@10014000
|
|
10020000 - 10021000 ARW gps-acq@10020000
|
|
10021000 - 10022000 ARW gps-tracking0@10021000
|
|
10022000 - 10023000 ARW gps-tracking1@10022000
|
|
10023000 - 10024000 ARW gps-tracking2@10023000
|
|
10024000 - 10025000 ARW gps-tracking3@10024000
|
|
10025000 - 10026000 ARW gps-tracking4@10025000
|
|
10026000 - 10027000 ARW gps-tracking5@10026000
|
|
10027000 - 10028000 ARW gps-tracking6@10027000
|
|
10028000 - 10029000 ARW gps-tracking7@10028000
|
|
10029000 - 1002a000 ARW gps-tracking8@10029000
|
|
80000000 - 80100000 ARWX dtim@80000000
|
|
|
|
[warn] hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 80:43: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0).
|
|
[warn] when (a_first && in.a.fire) { flight(in.a.bits.source) := !a_notFIFO }
|
|
[warn] ^
|
|
[warn] hardware/upstream/rocket-chip/src/main/scala/tilelink/FIFOFixer.scala 81:43: [W004] Dynamic index with width 1 is too wide for Vec of size 1 (expected index width 0).
|
|
[warn] when (d_first && in.d.fire) { flight(in.d.bits.source) := false.B }
|
|
[warn] ^
|
|
[warn] hardware/upstream/rocket-chip/src/main/scala/rocket/ICache.scala 508:25: [W002] Dynamic index with width 7 is too large for extractee of width 64
|
|
[warn] val s1_vb = vb_array(Cat(i.U, s1_idx).pad(log2Ceil(nSets*nWays))) && !s1_slaveValid
|
|
[warn] ^
|
|
[warn] There were 3 warning(s) during hardware elaboration.
|
|
|
|
****** Vivado v2025.2 (64-bit)
|
|
**** SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
|
|
**** IP Build 6300035 on Fri Nov 14 10:48:45 MST 2025
|
|
**** SharedData Build 6298862 on Thu Nov 13 04:50:51 MST 2025
|
|
**** Start of session at: Tue Jul 7 17:32:55 2026
|
|
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
|
** Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
|
|
|
|
Sourcing tcl script '/home/onur/.Xilinx/Vivado/Vivado_init.tcl'
|
|
Configured Digilent board repo: /home/onur/.local/share/digilent-vivado-boards/new/board_files
|
|
source /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/flow/vivado/scripts/build.tcl
|
|
# set script_dir [file dirname [file normalize [info script]]]
|
|
# set fpga_dir [file normalize [file join $script_dir ../../..]]
|
|
# set repo_dir [file normalize [file join $fpga_dir ../../..]]
|
|
# set hardware_dir [file join $repo_dir hardware]
|
|
# cd $repo_dir
|
|
# set part_name "xc7k325tffg900-2"
|
|
# set board_part "digilentinc.com:genesys2:part0:1.1"
|
|
# set top_module "genesys2_rocket_top"
|
|
# set out_dir [file join $fpga_dir out]
|
|
# set generated_dir [file join $out_dir build generated]
|
|
# set report_dir [file join $out_dir reports]
|
|
# set bit_dir [file join $out_dir bitstream]
|
|
# set checkpoint_dir [file join $out_dir build checkpoints]
|
|
# file mkdir $generated_dir
|
|
# file mkdir $report_dir
|
|
# file mkdir $bit_dir
|
|
# file mkdir $checkpoint_dir
|
|
# set rocket_rtl_dir [file join $hardware_dir generated genesys2-soc-verilog]
|
|
# set rocket_top [file join $rocket_rtl_dir VCU118RocketSystem.sv]
|
|
# set rocket_filelist [file join $rocket_rtl_dir filelist.f]
|
|
# set wrapper [file join $generated_dir ${top_module}.sv]
|
|
# if {[info exists ::env(GPS_SYSTEM_DIR)] && [string trim $::env(GPS_SYSTEM_DIR)] ne ""} {
|
|
# set gps_system_dir [file normalize $::env(GPS_SYSTEM_DIR)]
|
|
# } else {
|
|
# set gps_system_dir [file join $hardware_dir external gps rtl]
|
|
# }
|
|
# if {[info exists ::env(RF_INPUT_MODE)]} {
|
|
# set rf_input_mode [string tolower [string trim $::env(RF_INPUT_MODE)]]
|
|
# } else {
|
|
# set rf_input_mode "pmod"
|
|
# }
|
|
# if {$rf_input_mode ni {"pmod" "generated" "ethernet"}} {
|
|
# error "Unsupported Genesys2 RF_INPUT_MODE=$rf_input_mode. Use pmod, generated, or ethernet."
|
|
# }
|
|
# if {![file exists $rocket_filelist]} {
|
|
# error "Rocket Verilog filelist not found: $rocket_filelist"
|
|
# }
|
|
# if {![file exists $rocket_top]} {
|
|
# error "Rocket top Verilog not found: $rocket_top"
|
|
# }
|
|
# puts "Generating Genesys2 wrapper: $wrapper"
|
|
Generating Genesys2 wrapper: /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv
|
|
# puts "Genesys2 RF input mode: $rf_input_mode"
|
|
Genesys2 RF input mode: pmod
|
|
# exec python3 [file join $fpga_dir tools gen_genesys2_wrapper.py] \
|
|
# --rocket-top $rocket_top \
|
|
# --out $wrapper \
|
|
# --rf-input-mode $rf_input_mode
|
|
# set max_threads [string trim [exec nproc]]
|
|
# puts "Using Vivado maxThreads=$max_threads"
|
|
Using Vivado maxThreads=12
|
|
# set_param general.maxThreads $max_threads
|
|
# set_part $part_name
|
|
INFO: [Coretcl 2-1500] The part has been set to 'xc7k325tffg900-2' for the current project only. Run set_part -help for more details. To evaluate different speed grades in the current design, use the set_speed_grade command, or use the open_checkpoint -part command to change the part used by an existing checkpoint design.
|
|
# if {[llength [get_board_parts -quiet $board_part]] != 0} {
|
|
# set_property board_part $board_part [current_project]
|
|
# }
|
|
# proc apply_genesys2_async_clock_groups {} {
|
|
# set fabric_clk [get_clocks -quiet pll_fabric_clk]
|
|
# set gps_acq_clk [get_clocks -quiet pll_gps_acq_clk]
|
|
# set gps_trck_clk [get_clocks -quiet pll_gps_trck_clk]
|
|
# set gps_rf_clk [get_clocks -quiet {pll_gps_rf_exact_clk pmod_rf_clk}]
|
|
# set eth_clk [get_clocks -quiet genesys2_eth_rxck]
|
|
#
|
|
# if {[llength $fabric_clk] == 0 ||
|
|
# [llength $gps_acq_clk] == 0 ||
|
|
# [llength $gps_trck_clk] == 0 ||
|
|
# [llength $gps_rf_clk] == 0} {
|
|
# puts "Warning: not all Genesys2 async clock groups are available yet."
|
|
# return
|
|
# }
|
|
#
|
|
# puts "Applying Genesys2 async clock groups."
|
|
# set args [list -asynchronous \
|
|
# -group $fabric_clk \
|
|
# -group $gps_acq_clk \
|
|
# -group $gps_trck_clk \
|
|
# -group $gps_rf_clk]
|
|
# if {[llength $eth_clk] != 0} {
|
|
# lappend args -group $eth_clk
|
|
# }
|
|
# set_clock_groups {*}$args
|
|
# }
|
|
# set rocket_files {}
|
|
# set fh [open $rocket_filelist r]
|
|
# while {[gets $fh line] >= 0} {
|
|
# set line [string trim $line]
|
|
# if {$line eq ""} {
|
|
# continue
|
|
# }
|
|
# set line [regsub {^\./} $line ""]
|
|
# lappend rocket_files [file normalize [file join $rocket_rtl_dir $line]]
|
|
# }
|
|
# close $fh
|
|
# puts "Reading Rocket Chip RTL..."
|
|
Reading Rocket Chip RTL...
|
|
# read_verilog -sv $rocket_files
|
|
# read_verilog [file join $hardware_dir upstream rocket-chip src main resources vsrc plusarg_reader.v]
|
|
# set gps_filelist [file join $hardware_dir external gps rtl filelist.f]
|
|
# set gps_files {}
|
|
# set gps_fh [open $gps_filelist r]
|
|
# while {[gets $gps_fh rel] >= 0} {
|
|
# set rel [string trim $rel]
|
|
# if {$rel eq "" || [string match "#*" $rel]} {
|
|
# continue
|
|
# }
|
|
# lappend gps_files [file join $gps_system_dir $rel]
|
|
# }
|
|
# close $gps_fh
|
|
# puts "Reading GPS APB wrapper RTL from $gps_system_dir..."
|
|
Reading GPS APB wrapper RTL from /home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl...
|
|
# set_property include_dirs [list [file join $gps_system_dir trck_src pulp_fifo]] [current_fileset]
|
|
# read_verilog -sv $gps_files
|
|
# puts "Reading Genesys2 shell RTL..."
|
|
Reading Genesys2 shell RTL...
|
|
# set shell_files [list \
|
|
# [file join $hardware_dir fpga vcu118 rtl axi4_ram_64.sv] \
|
|
# [file join $hardware_dir fpga vcu118 rtl axi4_slave_tieoff_64.sv] \
|
|
# [file join $hardware_dir fpga genesys2 rtl rocket_bscan_dmi_tunnel.sv] \
|
|
# ]
|
|
# if {$rf_input_mode eq "ethernet"} {
|
|
# puts "Reading Genesys2 Ethernet RF RTL..."
|
|
# lappend shell_files \
|
|
# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_async_fifo.sv] \
|
|
# [file join $hardware_dir fpga vcu118 rtl ethernet_rf eth_rf_core.sv] \
|
|
# [file join $hardware_dir fpga genesys2 rtl ethernet_rf eth_rf_genesys2.sv]
|
|
# } else {
|
|
# puts "Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=$rf_input_mode."
|
|
# }
|
|
Skipping Genesys2 Ethernet RF RTL for RF_INPUT_MODE=pmod.
|
|
# read_verilog -sv $shell_files
|
|
# read_verilog -sv $wrapper
|
|
# puts "Reading constraints..."
|
|
Reading constraints...
|
|
# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_rocket.xdc]
|
|
# if {$rf_input_mode eq "pmod"} {
|
|
# puts "Reading Genesys2 PMOD RF constraints..."
|
|
# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_pmod_rf.xdc]
|
|
# } elseif {$rf_input_mode eq "ethernet"} {
|
|
# puts "Reading Genesys2 Ethernet PHY constraints..."
|
|
# read_xdc [file join $hardware_dir fpga genesys2 constraints genesys2_ethernet.xdc]
|
|
# }
|
|
Reading Genesys2 PMOD RF constraints...
|
|
# puts "Running synthesis for $part_name..."
|
|
Running synthesis for xc7k325tffg900-2...
|
|
# synth_design -top $top_module -part $part_name -verilog_define SYNTHESIS
|
|
Command: synth_design -top genesys2_rocket_top -part xc7k325tffg900-2 -verilog_define SYNTHESIS
|
|
Starting synth_design
|
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
|
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
|
|
INFO: [Device 21-403] Loading part xc7k325tffg900-2
|
|
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 7 processes.
|
|
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
|
INFO: [Synth 8-7075] Helper process launched with PID 4440
|
|
---------------------------------------------------------------------------------
|
|
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 2352.348 ; gain = 482.844 ; free physical = 11699 ; free virtual = 19992
|
|
---------------------------------------------------------------------------------
|
|
WARNING: [Synth 8-11067] parameter 'CODE_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:8]
|
|
WARNING: [Synth 8-11067] parameter 'CODE_LENGTH_IN_CHIPS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:9]
|
|
WARNING: [Synth 8-11067] parameter 'DOPPLER_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:10]
|
|
WARNING: [Synth 8-11067] parameter 'SAMPLING_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:13]
|
|
WARNING: [Synth 8-11067] parameter 'CENTER_FREQ' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:14]
|
|
WARNING: [Synth 8-11067] parameter 'RF_DATA_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:15]
|
|
WARNING: [Synth 8-11067] parameter 'RF_DATA_RANGE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:16]
|
|
WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:17]
|
|
WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:18]
|
|
WARNING: [Synth 8-11067] parameter 'SAMPLE_ALIGN_NUM_WAIT_SAMP_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:19]
|
|
WARNING: [Synth 8-11067] parameter 'ABS_SAMPLE_CNTR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:22]
|
|
WARNING: [Synth 8-11067] parameter 'MS_PER_BIT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:23]
|
|
WARNING: [Synth 8-11067] parameter 'C_ACQ_CHN_NUM' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:26]
|
|
WARNING: [Synth 8-11067] parameter 'ACQ_IQ_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:27]
|
|
WARNING: [Synth 8-11067] parameter 'ACQ_CORR_DWIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:28]
|
|
WARNING: [Synth 8-11067] parameter 'RF_DMEM_AL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:30]
|
|
WARNING: [Synth 8-11067] parameter 'NUM_PRN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:31]
|
|
WARNING: [Synth 8-11067] parameter 'PRN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:32]
|
|
WARNING: [Synth 8-11067] parameter 'STRECH_COUNT_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:33]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_COEF1' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:40]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:41]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:42]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:43]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:44]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:45]
|
|
WARNING: [Synth 8-11067] parameter 'TRCK_CARR_NCO_FREQ_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:46]
|
|
WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:47]
|
|
WARNING: [Synth 8-11067] parameter 'ACQUIRED_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:48]
|
|
WARNING: [Synth 8-11067] parameter 'NUM_TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:50]
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WARNING: [Synth 8-11067] parameter 'TRCK_SINWAV_LUT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:51]
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WARNING: [Synth 8-11067] parameter 'ATAN_ANGLE_BIT_WIDTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:56]
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WARNING: [Synth 8-11067] parameter 'ATAN_TABLE_SIZE' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:57]
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WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:60]
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WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:61]
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WARNING: [Synth 8-11067] parameter 'CARR_NCO_COEF1_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:62]
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WARNING: [Synth 8-11067] parameter 'DOPPLER_SPACE_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:63]
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WARNING: [Synth 8-11067] parameter 'C1_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:65]
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WARNING: [Synth 8-11067] parameter 'C2_CARR' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:66]
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WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:71]
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WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:72]
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WARNING: [Synth 8-11067] parameter 'DLL_DISC_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:73]
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WARNING: [Synth 8-11067] parameter 'SMOOTH_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:76]
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WARNING: [Synth 8-11067] parameter 'SMOOTH_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:77]
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WARNING: [Synth 8-11067] parameter 'SMOOTH_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:78]
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WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:80]
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WARNING: [Synth 8-11067] parameter 'SMOOTH_DIFF_INT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:81]
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WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:83]
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WARNING: [Synth 8-11067] parameter 'LOCK_DET_DIV_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:84]
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WARNING: [Synth 8-11067] parameter 'LOCK_WINDOW' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:85]
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WARNING: [Synth 8-11067] parameter 'LOCK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:86]
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WARNING: [Synth 8-11067] parameter 'DLL_LF_O_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:89]
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WARNING: [Synth 8-11067] parameter 'DLL_LF_O_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:90]
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WARNING: [Synth 8-11067] parameter 'C1_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:92]
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WARNING: [Synth 8-11067] parameter 'C2_CODE_REAL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:93]
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WARNING: [Synth 8-11067] parameter 'C1_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:95]
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WARNING: [Synth 8-11067] parameter 'C2_CODE_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:96]
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WARNING: [Synth 8-11067] parameter 'CODE_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:99]
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WARNING: [Synth 8-11067] parameter 'CODE_FREQ_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:100]
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WARNING: [Synth 8-11067] parameter 'REAL_POS_FS_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:102]
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WARNING: [Synth 8-11067] parameter 'REAL_NEG_FS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:103]
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WARNING: [Synth 8-11067] parameter 'FS_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:105]
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WARNING: [Synth 8-11067] parameter 'DLL_FREQ_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:106]
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WARNING: [Synth 8-11067] parameter 'DLL_SPACING' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:108]
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WARNING: [Synth 8-11067] parameter 'DLL_SPACING_RDX_ALIGNED' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:109]
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WARNING: [Synth 8-11067] parameter 'TRCK_CORR_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:112]
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WARNING: [Synth 8-11067] parameter 'TRCK_CORR_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:113]
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WARNING: [Synth 8-11067] parameter 'TRCK_CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:114]
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WARNING: [Synth 8-11067] parameter 'F_ACQ_CLK' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:117]
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WARNING: [Synth 8-11067] parameter 'ACQ_CLK_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:118]
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WARNING: [Synth 8-11067] parameter 'RF_PERIOD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:119]
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WARNING: [Synth 8-11067] parameter 'SAMPLES_PER_CODE_CHIP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:120]
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WARNING: [Synth 8-11067] parameter 'ACQ_NCO_PH_ACC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:122]
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WARNING: [Synth 8-11067] parameter 'ACQ_SIN_IL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:123]
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WARNING: [Synth 8-11067] parameter 'ACQ_SIN_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:124]
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WARNING: [Synth 8-11067] parameter 'ACQ_SIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:125]
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WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:126]
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WARNING: [Synth 8-11067] parameter 'ACQ_SIN_LUT_DEPTH_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:127]
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WARNING: [Synth 8-11067] parameter 'ACQ_CODE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:129]
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WARNING: [Synth 8-11067] parameter 'FFT_IQ_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:131]
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WARNING: [Synth 8-11067] parameter 'FFT_IQ_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:132]
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WARNING: [Synth 8-11067] parameter 'FFT_CODE_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:133]
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WARNING: [Synth 8-11067] parameter 'FFT_CODE_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:134]
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WARNING: [Synth 8-11067] parameter 'IFFT_TWIDDLE_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:135]
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WARNING: [Synth 8-11067] parameter 'IFFT_FRAC_BITS' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:136]
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WARNING: [Synth 8-11067] parameter 'IFFT_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:138]
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WARNING: [Synth 8-11067] parameter 'NFFT' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:140]
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WARNING: [Synth 8-11067] parameter 'NFFT_OVER_2' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:141]
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WARNING: [Synth 8-11067] parameter 'ZERO_PAD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:142]
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WARNING: [Synth 8-11067] parameter 'IFFT_O_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:144]
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WARNING: [Synth 8-11067] parameter 'IFFT_O_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:145]
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WARNING: [Synth 8-11067] parameter 'ABS_SQR_I_TRUNCATED_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:146]
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WARNING: [Synth 8-11067] parameter 'CORR_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:147]
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WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_DIV_I_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:148]
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WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:149]
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WARNING: [Synth 8-11067] parameter 'PEAK_METRIC_FL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:150]
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WARNING: [Synth 8-11067] parameter 'PEAK_THRESHOLD' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:151]
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WARNING: [Synth 8-11067] parameter 'DOPP_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:153]
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WARNING: [Synth 8-11067] parameter 'NUM_FREQ_BIN' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:154]
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WARNING: [Synth 8-11067] parameter 'FREQ_BIN_WL' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:155]
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WARNING: [Synth 8-11067] parameter 'PULLIN_FREQ_STEP' declared inside package 'definitions' shall be treated as localparam [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/definitions.sv:157]
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INFO: [Common 17-14] Message 'Synth 8-11067' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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WARNING: [Synth 8-10180] variable 'i' must explicitly be declared as automatic or static [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/acq_nco_carr.sv:53]
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INFO: [Synth 8-6157] synthesizing module 'genesys2_rocket_top' [/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:3]
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INFO: [Synth 8-6157] synthesizing module 'IBUFDS' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
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Parameter DIFF_TERM bound to: FALSE - type: string
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Parameter IBUF_LOW_PWR bound to: FALSE - type: string
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INFO: [Synth 8-6155] done synthesizing module 'IBUFDS' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82819]
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INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
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Parameter BANDWIDTH bound to: OPTIMIZED - type: string
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Parameter CLKFBOUT_MULT_F bound to: 5.000000e+00 - type: double
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Parameter CLKFBOUT_PHASE bound to: 0.000000e+00 - type: double
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Parameter CLKIN1_PERIOD bound to: 5.000000e+00 - type: double
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Parameter CLKIN2_PERIOD bound to: 0.000000e+00 - type: double
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Parameter CLKOUT0_DIVIDE_F bound to: 1.250000e+01 - type: double
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Parameter CLKOUT0_DUTY_CYCLE bound to: 5.000000e-01 - type: double
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Parameter CLKOUT0_PHASE bound to: 0.000000e+00 - type: double
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Parameter CLKOUT1_DIVIDE bound to: 20 - type: integer
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Parameter CLKOUT1_DUTY_CYCLE bound to: 5.000000e-01 - type: double
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Parameter CLKOUT1_PHASE bound to: 0.000000e+00 - type: double
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Parameter CLKOUT2_DIVIDE bound to: 8 - type: integer
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Parameter CLKOUT2_DUTY_CYCLE bound to: 5.000000e-01 - type: double
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Parameter CLKOUT2_PHASE bound to: 0.000000e+00 - type: double
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Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
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Parameter REF_JITTER1 bound to: 1.000000e-02 - type: double
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Parameter REF_JITTER2 bound to: 1.000000e-02 - type: double
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Parameter STARTUP_WAIT bound to: FALSE - type: string
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INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:95844]
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WARNING: [Synth 8-7071] port 'CLKFBSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:61]
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WARNING: [Synth 8-7071] port 'CLKINSTOPPED' of module 'MMCME2_ADV' is unconnected for instance 'u_clock_mmcm' [/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:61]
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WARNING: [Synth 8-7023] instance 'u_clock_mmcm' of module 'MMCME2_ADV' has 33 connections declared, but only 31 given [/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:61]
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INFO: [Synth 8-6157] synthesizing module 'BUFG' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
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INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2678]
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INFO: [Synth 8-6157] synthesizing module 'IBUF' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
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INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:82804]
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INFO: [Synth 8-6157] synthesizing module 'BSCANE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
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Parameter DISABLE_JTAG bound to: FALSE - type: string
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Parameter JTAG_CHAIN bound to: 4 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'BSCANE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:2479]
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INFO: [Synth 8-6157] synthesizing module 'rocket_bscan_dmi_tunnel' [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
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INFO: [Synth 8-6155] done synthesizing module 'rocket_bscan_dmi_tunnel' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/rtl/rocket_bscan_dmi_tunnel.sv:3]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/generated/genesys2_rocket_top.sv:256]
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INFO: [Synth 8-6157] synthesizing module 'STARTUPE2' [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
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Parameter PROG_USR bound to: FALSE - type: string
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Parameter SIM_CCLK_FREQ bound to: 0.000000e+00 - type: double
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INFO: [Synth 8-6155] done synthesizing module 'STARTUPE2' (0#1) [/tools/Xilinx/2025.2/Vivado/scripts/rt/data/unisim_comp.v:165504]
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INFO: [Synth 8-6157] synthesizing module 'VCU118RocketSystem' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/VCU118RocketSystem.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ClockSinkDomain' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'IntXbar_i1_o1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i1_o1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i1_o1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i1_o1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ClockSinkDomain' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockSinkDomain.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_aggregator' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_aggregator' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_aggregator.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'SystemBus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_sbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_sbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_sbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ClockGroup' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ClockGroup' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroup.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_3' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_3' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_3.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_sbus_i2_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_sbus_i2_o1_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_to_bus_named_cbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_to_bus_named_cbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_bus_named_fbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_bus_named_fbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_sbus_from_rockettile' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_sbus_from_rockettile.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'SystemBus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/SystemBus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_pbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_pbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_pbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_pbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_4' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_4.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_4' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_4.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_1.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_in_i1_o1_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_in_i1_o1_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_pbus_out_i1_o3_a29d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_pbus_out_i1_o3_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_pbus_out_i1_o3_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a29d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ram_2x120' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'ram_2x120' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x120.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ram_2x77' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'ram_2x77' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x77.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_pbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_pbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_pbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAUART' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAUART' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAUART.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_fpga_uart' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_fpga_uart.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_pbus_to_gps' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_FPGAGPS' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d32s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d32s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_FPGAGPS' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_FPGAGPS.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_2' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_2' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a29d64s2k1z3u_2' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a29d64s2k1z3u_2.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_2' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_2.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_pbus_to_gps' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_pbus_to_gps.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_pbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_pbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'FrontBus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_1.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_fbus_i1_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_fbus_i1_o1_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s1k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ram_2x123' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'ram_2x123' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x123.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleD_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleD_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_fbus_from_debug_sb' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_fbus_from_debug_sb.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'FrontBus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FrontBus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'PeripheryBus_cbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ClockGroupAggregator_cbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ClockGroupAggregator_cbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ClockGroupAggregator_cbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'FixedClockBroadcast_5' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'FixedClockBroadcast_5' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/FixedClockBroadcast_5.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFIFOFixer_2' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFIFOFixer_2' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFIFOFixer_2.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_in_i1_o1_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_in_i1_o1_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_cbus_out_i1_o7_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_cbus_out_i1_o7_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ram_2x124' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'ram_2x124' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x124.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ram_2x78' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'ram_2x78' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x78.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleD_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleD_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLAtomicAutomata_cbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLAtomicAutomata_cbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLAtomicAutomata_cbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ErrorDeviceWrapper' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLError' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Queue1_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue1_TLBundleA_a14d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLError' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a14d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'ram_2x99' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'ram_2x99' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ram_2x99.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'Queue2_TLBundleA_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Queue2_TLBundleA_a14d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a14d64s2k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a14d64s2k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'ErrorDeviceWrapper' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ErrorDeviceWrapper.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLBuffer_a32d64s2k1z4u_1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLBuffer_a32d64s2k1z4u_1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLBuffer_a32d64s2k1z4u_1.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_3' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_3' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_3.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bus_named_pbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bus_named_pbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_clint' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_CLINT' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a26d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a26d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_CLINT' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_CLINT.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_clint' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_clint.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_plic' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_PLIC' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a28d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a28d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_PLIC' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_PLIC.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_plic' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_plic.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_debug' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_Debug' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a12d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a12d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_Debug' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_Debug.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_debug' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_debug.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLWidthWidget8_4' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLWidthWidget8_4' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLWidthWidget8_4.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_rockettile' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_rockettile.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLFragmenter_bootrom' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Repeater_TLBundleA_a17d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Repeater_TLBundleA_a17d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLFragmenter_bootrom' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLFragmenter_bootrom.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLInterconnectCoupler_cbus_to_bootrom' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLInterconnectCoupler_cbus_to_bootrom.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'PeripheryBus_cbus' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PeripheryBus_cbus.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TilePRCIDomain' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'HierarchicalElementResetDomain' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/HierarchicalElementResetDomain.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'RocketTile' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/RocketTile.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_MasterXbar_RocketTile_i2_o1_a32d64s1k1z4u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLXbar_SlaveXbar_RocketTile_i1_o1_a32d64s2k1z3u.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'IntXbar_i3_o1' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'IntXbar_i3_o1' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/IntXbar_i3_o1.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'DCache' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'DTLB' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'PMPChecker_s3' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'PMPChecker_s3' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PMPChecker_s3.sv:31]
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INFO: [Synth 8-6157] synthesizing module 'PMAChecker' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'PMAChecker' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PMAChecker.sv:31]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:194]
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INFO: [Synth 8-6157] synthesizing module 'OptimizationBarrier_TLBEntryData' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'OptimizationBarrier_TLBEntryData' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/OptimizationBarrier_TLBEntryData.sv:31]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:228]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:262]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:296]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:330]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:364]
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INFO: [Synth 8-6155] done synthesizing module 'DTLB' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DTLB.sv:31]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:1121]
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INFO: [Synth 8-6157] synthesizing module 'Arbiter8_DCacheMetadataReq' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
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INFO: [Common 17-14] Message 'Synth 8-6157' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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INFO: [Synth 8-6155] done synthesizing module 'Arbiter8_DCacheMetadataReq' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter8_DCacheMetadataReq.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'rockettile_dcache_data_arrays_0_131072x64' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:32]
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INFO: [Synth 8-6155] done synthesizing module 'DCacheDataArray' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DCacheDataArray.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'Arbiter4_DCacheDataReq' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Arbiter4_DCacheDataReq.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'AMOALU' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/AMOALU.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'DCache' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:31]
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INFO: [Synth 8-6155] done synthesizing module 'rockettile_icache_tag_array_0_64x21' (0#1) [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:32]
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INFO: [Common 17-14] Message 'Synth 8-6155' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:139]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:173]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:207]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:241]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:275]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/ITLB.sv:309]
|
|
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/PTW.sv:188]
|
|
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:3191]
|
|
Parameter FORMAT bound to: max_core_cycles=%d - type: string
|
|
Parameter WIDTH bound to: 32 - type: integer
|
|
Parameter DEFAULT bound to: 32'b00000000000000000000000000000000
|
|
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:400]
|
|
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:406]
|
|
WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TilePRCIDomain.sv:412]
|
|
Parameter HIGH_ADDRESS bound to: 4095 - type: integer
|
|
Parameter LOW_ADDRESS bound to: 0 - type: integer
|
|
Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
|
|
Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
|
|
Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000000001
|
|
Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
|
|
Parameter DATA_WIDTH bound to: 4 - type: integer
|
|
Parameter ADDR_WIDTH bound to: 15 - type: integer
|
|
Parameter PH_ACC_WL bound to: 32 - type: integer
|
|
Parameter LUT_DEPTH_WL bound to: 5 - type: integer
|
|
Parameter ACQ_SIN_IL bound to: 2 - type: integer
|
|
Parameter ACQ_SIN_FL bound to: 4 - type: integer
|
|
Parameter PH_ACC_WL bound to: 25 - type: integer
|
|
Parameter FS bound to: 16368000 - type: integer
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter DATA_WIDTH bound to: 10 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FRAC_BITS bound to: 2 - type: integer
|
|
Parameter DATA_WIDTH bound to: 10 - type: integer
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FRAC_BITS bound to: 2 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter DATA_WIDTH bound to: 52 - type: integer
|
|
Parameter ADDR_WIDTH bound to: 14 - type: integer
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter DATA_WIDTH bound to: 2 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FRAC_BITS bound to: 2 - type: integer
|
|
Parameter DATA_WIDTH bound to: 2 - type: integer
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FRAC_BITS bound to: 2 - type: integer
|
|
Parameter DATA_WIDTH bound to: 36 - type: integer
|
|
Parameter ADDR_WIDTH bound to: 14 - type: integer
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
|
|
Parameter FFT_IQ_WL bound to: 24 - type: integer
|
|
Parameter FFT_IQ_TRUNC_WL bound to: 20 - type: integer
|
|
Parameter FFT_CODE_WL bound to: 16 - type: integer
|
|
Parameter FFT_CODE_TRUNC_WL bound to: 16 - type: integer
|
|
Parameter OUT_WL bound to: 30 - type: integer
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter DATA_WIDTH bound to: 30 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FRAC_BITS bound to: 2 - type: integer
|
|
Parameter DATA_WIDTH bound to: 30 - type: integer
|
|
Parameter FFT_POWER bound to: 14 - type: integer
|
|
Parameter TWIDDLE_WIDTH bound to: 15 - type: integer
|
|
Parameter FRAC_BITS bound to: 2 - type: integer
|
|
Parameter DATA_WIDTH bound to: 92 - type: integer
|
|
Parameter ADDR_WIDTH bound to: 14 - type: integer
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:126]
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:170]
|
|
Parameter DWIDTH bound to: 48 - type: integer
|
|
Parameter AWIDTH bound to: 14 - type: integer
|
|
Parameter ABS_SQR_I_TRUNCATED_WL bound to: 25 - type: integer
|
|
Parameter CORR_DWIDTH bound to: 51 - type: integer
|
|
Parameter AWIDTH bound to: 14 - type: integer
|
|
Parameter SAMPLES_PER_CODE_CHIP bound to: 16 - type: integer
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/acq_peak_srch.sv:158]
|
|
Parameter DWIDTH bound to: 51 - type: integer
|
|
Parameter AWIDTH bound to: 14 - type: integer
|
|
Parameter ITER bound to: 9 - type: integer
|
|
Parameter IN_W_L bound to: 36 - type: integer
|
|
Parameter IN_F_L bound to: 0 - type: integer
|
|
Parameter OUT_W_L bound to: 16 - type: integer
|
|
Parameter OUT_F_L bound to: 8 - type: integer
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:285]
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:296]
|
|
WARNING: [Synth 8-151] case item 32'b00000000000000000000000000001100 is unreachable [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/apb_wrappers/acqusition_wrapper.sv:350]
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|
WARNING: [Synth 8-7071] port 'clk_200mhz' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'mmcm_locked' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'eth_rgmii_rd' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'eth_rgmii_rx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'eth_rgmii_rxc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'eth_rgmii_td' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'eth_rgmii_tx_ctl' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7071] port 'eth_rgmii_txc' of module 'afe_top' is unconnected for instance 'afe' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
WARNING: [Synth 8-7023] instance 'afe' of module 'afe_top' has 17 connections declared, but only 9 given [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/APBGpsBlock.sv:135]
|
|
Parameter HIGH_ADDRESS bound to: 4095 - type: integer
|
|
Parameter LOW_ADDRESS bound to: 0 - type: integer
|
|
Parameter DATA_BUS_WIDTH bound to: 32 - type: integer
|
|
Parameter ADDR_BUS_WIDTH bound to: 12 - type: integer
|
|
Parameter SIG_DEPTH bound to: 32'b00000000000000000000000000100000
|
|
Parameter PIP_LENGTH bound to: 32'b00000000000000000000000000000010
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:182]
|
|
Parameter WIDTH bound to: 4 - type: integer
|
|
Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
|
|
Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
|
|
Parameter STAGES bound to: 32'b00000000000000000000000000000010
|
|
Parameter N bound to: 32'sb00000000000000000000000000000101
|
|
Parameter N bound to: 32'sb00000000000000000000000000000101
|
|
Parameter LOG_DEPTH bound to: 32'sb00000000000000000000000000000100
|
|
Parameter Bypass bound to: 1'b0
|
|
Parameter PH_ACC_WL bound to: 24 - type: integer
|
|
Parameter LUT_DEPTH_WL bound to: 7 - type: integer
|
|
Parameter SIN_IL bound to: 2 - type: integer
|
|
Parameter SIN_FL bound to: 4 - type: integer
|
|
Parameter PH_ACC_WL bound to: 46 - type: integer
|
|
Parameter CODE_FREQ_I_IL bound to: 21 - type: integer
|
|
Parameter CODE_FREQ_I_FL bound to: 20 - type: integer
|
|
Parameter ERROR_I_IL bound to: 2 - type: integer
|
|
Parameter ERROR_I_FL bound to: 10 - type: integer
|
|
Parameter O_IL bound to: 16 - type: integer
|
|
Parameter ERROR_I_IL bound to: 2 - type: integer
|
|
Parameter ERROR_I_FL bound to: 13 - type: integer
|
|
Parameter O_IL bound to: 8 - type: integer
|
|
Parameter O_FL bound to: 20 - type: integer
|
|
Parameter TABLE_SIZE bound to: 9 - type: integer
|
|
Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
|
|
Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
|
|
Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
|
|
Parameter TABLE_ADDR bound to: 4 - type: integer
|
|
Parameter TABLE_SIZE bound to: 9 - type: integer
|
|
Parameter ANGLE_BIT_WIDTH bound to: 12 - type: integer
|
|
Parameter COORD_BIT_WIDTH bound to: 33 - type: integer
|
|
WARNING: [Synth 8-7071] port 'vec_len_o' of module 'cordic_atan_basic' is unconnected for instance 'Disc_PLL_i' [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:213]
|
|
WARNING: [Synth 8-7023] instance 'Disc_PLL_i' of module 'cordic_atan_basic' has 8 connections declared, but only 7 given [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:213]
|
|
Parameter IN_WL bound to: 22 - type: integer
|
|
Parameter IN_FL bound to: 4 - type: integer
|
|
Parameter OUT_WL bound to: 15 - type: integer
|
|
Parameter OUT_FL bound to: 13 - type: integer
|
|
Parameter ITER1 bound to: 8 - type: integer
|
|
Parameter ITER2 bound to: 14 - type: integer
|
|
Parameter TABLE_SIZE bound to: 8 - type: integer
|
|
Parameter COORD_BIT_WIDTH bound to: 22 - type: integer
|
|
Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
|
|
Parameter TABLE_ADDR bound to: 3 - type: integer
|
|
WARNING: [Synth 8-151] case item 4'b1000 is unreachable [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:114]
|
|
INFO: [Synth 8-226] default block is never used [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_angle_lut.sv:105]
|
|
Parameter TABLE_SIZE bound to: 8 - type: integer
|
|
Parameter ANGLE_BIT_WIDTH bound to: 32 - type: integer
|
|
Parameter COORD_BIT_WIDTH bound to: 32 - type: integer
|
|
Parameter ITER bound to: 14 - type: integer
|
|
Parameter IN_WL bound to: 25 - type: integer
|
|
Parameter IN_FL bound to: 4 - type: integer
|
|
Parameter OUT_WL bound to: 15 - type: integer
|
|
Parameter OUT_FL bound to: 13 - type: integer
|
|
Parameter IN_WL bound to: 22 - type: integer
|
|
Parameter IN_FL bound to: 4 - type: integer
|
|
Parameter DIV_OUT_WL bound to: 15 - type: integer
|
|
Parameter DIV_OUT_FL bound to: 13 - type: integer
|
|
Parameter DIV_ITER bound to: 14 - type: integer
|
|
Parameter IN_WL bound to: 22 - type: integer
|
|
Parameter IN_FL bound to: 4 - type: integer
|
|
Parameter OUT_WL bound to: 15 - type: integer
|
|
Parameter OUT_FL bound to: 13 - type: integer
|
|
Parameter ITER2 bound to: 14 - type: integer
|
|
Parameter ITER bound to: 14 - type: integer
|
|
Parameter IN_WL bound to: 45 - type: integer
|
|
Parameter IN_FL bound to: 8 - type: integer
|
|
Parameter OUT_WL bound to: 15 - type: integer
|
|
Parameter OUT_FL bound to: 13 - type: integer
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:273]
|
|
INFO: [Synth 8-155] case statement is not full and has no default [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/apb_wrappers/tracking_wrapper.sv:530]
|
|
WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:48]
|
|
WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_dcache_data_arrays_0_131072x64.sv:49]
|
|
WARNING: [Synth 8-6014] Unused sequential element s2_vaddr_r_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:989]
|
|
WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:47]
|
|
WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_tag_array_0_64x21.sv:48]
|
|
WARNING: [Synth 8-6014] Unused sequential element _RW0_ren_d0_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:47]
|
|
WARNING: [Synth 8-6014] Unused sequential element _RW0_rmode_d0_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/rockettile_icache_data_arrays_512x32.sv:48]
|
|
WARNING: [Synth 8-4767] Trying to implement RAM 'Memory_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/regfile_32x65.sv:60]
|
|
Reason is one or more of the following :
|
|
1: RAM has multiple writes via different ports in same process. If RAM inferencing intended, write to one port per process.
|
|
2: Invalid write to RAM.
|
|
3: Invalid write to RAM.
|
|
4: No valid clock found for write to RAM.
|
|
WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rxs1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2183]
|
|
WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2626]
|
|
WARNING: [Synth 8-6014] Unused sequential element ex_ctrl_rfs2_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2637]
|
|
WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs2_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2754]
|
|
WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rxs1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2755]
|
|
WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2757]
|
|
WARNING: [Synth 8-6014] Unused sequential element mem_ctrl_rfs2_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2758]
|
|
WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs2_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2769]
|
|
WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rxs1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2770]
|
|
WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2772]
|
|
WARNING: [Synth 8-6014] Unused sequential element wb_ctrl_rfs2_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2773]
|
|
WARNING: [Synth 8-6014] Unused sequential element rocc_blocked_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2894]
|
|
WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2895]
|
|
WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd0val_REG_1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2896]
|
|
WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2897]
|
|
WARNING: [Synth 8-6014] Unused sequential element coreMonitorBundle_rd1val_REG_1_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Rocket.sv:2898]
|
|
WARNING: [Synth 8-6014] Unused sequential element r_counter_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/TLError_1.sv:69]
|
|
Read & Write Range Direction Mismatch
|
|
Read & Write Range Direction Mismatch
|
|
WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module comp_mult has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/comp_mult.sv:106]
|
|
Read & Write Range Direction Mismatch
|
|
WARNING: [Synth 8-7137] Register mult_vld_reg_reg in module ifft_abs_sqr has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:90]
|
|
WARNING: [Synth 8-3848] Net eth_rgmii_td in module/entity afe_top does not have driver. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:38]
|
|
WARNING: [Synth 8-3848] Net eth_rgmii_tx_ctl in module/entity afe_top does not have driver. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:39]
|
|
WARNING: [Synth 8-3848] Net eth_rgmii_txc in module/entity afe_top does not have driver. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:40]
|
|
WARNING: [Synth 8-3848] Net rf_data_o in module/entity afe_top does not have driver. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/common/afe_top.sv:46]
|
|
WARNING: [Synth 8-3848] Net fifo_of_o in module/entity trck_cntrl does not have driver. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_cntrl.sv:50]
|
|
WARNING: [Synth 8-6014] Unused sequential element g1_var_reg was removed. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:46]
|
|
WARNING: [Synth 8-7137] Register chip_o_reg in module cacode_gen_trck has both Set and reset with same priority. This may cause simulation mismatches. Consider rewriting code [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/cacode_gen_trck.sv:36]
|
|
WARNING: [Synth 8-7129] Port fifo_of_o in module trck_cntrl is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port PENABLE in module tracking_wrapper is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_td[3] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_td[2] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_td[1] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_td[0] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_tx_ctl in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_txc in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port rf_data_o[3] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port rf_data_o[2] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port rf_data_o[1] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port rf_data_o[0] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port clk_200mhz in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port mmcm_locked in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_rd[3] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_rd[2] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_rd[1] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_rd[0] in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_rx_ctl in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port eth_rgmii_rxc in module afe_top is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port a_i[3] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port a_i[2] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port a_i[1] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port a_i[0] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port bi_i[3] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port bi_i[2] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port bi_i[1] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port bi_i[0] in module comp_mult is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port PENABLE in module acq_wrapper is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port start_acq_manuel in module acq_wrapper is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaSPI is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[28] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[27] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[26] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[25] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[24] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[23] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[22] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[21] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[20] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[19] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[18] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[17] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[15] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[14] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[13] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[12] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLFpgaUART is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[16] in module TLROM is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[2] in module TLROM is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[1] in module TLROM is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port auto_in_a_bits_address[0] in module TLROM is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port R0_en in module ram_2x10 is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port R0_clk in module ram_2x10 is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_opcode[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_opcode[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_opcode[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_param[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_param[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_size[3] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_size[2] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_size[1] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_size[0] in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_enq_bits_sink in module Queue2_TLBundleD_a32d8s1k1z4u is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[127] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[126] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[125] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[124] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[123] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[122] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[121] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[120] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[119] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[118] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[117] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[116] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[115] in module SBToTL is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port io_dataIn[114] in module SBToTL is either unconnected or has no load
|
|
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 2738.887 ; gain = 869.383 ; free physical = 11202 ; free virtual = 19589
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 2738.887 ; gain = 869.383 ; free physical = 11207 ; free virtual = 19597
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:10 ; elapsed = 00:00:16 . Memory (MB): peak = 2738.887 ; gain = 869.383 ; free physical = 11207 ; free virtual = 19597
|
|
---------------------------------------------------------------------------------
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.56 . Memory (MB): peak = 2738.887 ; gain = 0.000 ; free physical = 11202 ; free virtual = 19618
|
|
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
|
|
Processing XDC Constraints
|
|
Initializing timing engine
|
|
Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
|
|
Finished Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|
Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
|
|
Finished Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
|
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/genesys2_rocket_top_propImpl.xdc].
|
|
Resolution: To avoid this warning, move constraints listed in [.Xil/genesys2_rocket_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
|
INFO: [Timing 38-2] Deriving generated clocks
|
|
Completed Processing XDC Constraints
|
|
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2998.059 ; gain = 0.000 ; free physical = 11102 ; free virtual = 19573
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
No Unisim elements were transformed.
|
|
|
|
INFO: [Synth 8-3971] The signal "dual_port_bram:/ram_reg" was recognized as a true dual port RAM template.
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
FSM_IDLE | 00 | 00
|
|
FSM_SAVE_DATA | 01 | 01
|
|
FSM_CALC_FFT | 10 | 10
|
|
FSM_RELEASE_DATA | 11 | 11
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2'
|
|
INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized0:/ram_reg" was recognized as a true dual port RAM template.
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
FSM_IDLE | 00 | 00
|
|
FSM_SAVE_DATA | 01 | 01
|
|
FSM_CALC_FFT | 10 | 10
|
|
FSM_RELEASE_DATA | 11 | 11
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized0'
|
|
INFO: [Synth 8-3971] The signal "dual_port_bram__parameterized1:/ram_reg" was recognized as a true dual port RAM template.
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
FSM_IDLE | 00 | 00
|
|
FSM_SAVE_DATA | 01 | 01
|
|
FSM_CALC_FFT | 10 | 10
|
|
FSM_RELEASE_DATA | 11 | 11
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'FsmState_SP_reg' using encoding 'sequential' in module 'fft_radix_2__parameterized1'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
S_IDLE | 001 | 000
|
|
S_CORR | 101 | 001
|
|
S_INIT_ADDR | 100 | 010
|
|
S_DATA_Q | 011 | 011
|
|
S_SRCH | 010 | 100
|
|
S_END | 000 | 101
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'sequential' in module 'acq_peak_srch'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
idle | 00 | 00
|
|
normalization | 01 | 01
|
|
cordic_core | 10 | 10
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'divider_fsm'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
S_IDLE | 0000001 | 000
|
|
S_WR_DATA | 0001000 | 001
|
|
S_START | 0010000 | 010
|
|
S_CTRL | 1000000 | 011
|
|
S_FREQ | 0100000 | 100
|
|
S_END | 0000010 | 101
|
|
S_PULLIN | 0000100 | 110
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'STATE_reg' using encoding 'one-hot' in module 'acq_top'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
APB_STATE_IDLE | 001 | 00000000000000000000000000000000
|
|
APB_STATE_SEL | 010 | 00000000000000000000000000000001
|
|
APB_STATE_WR | 100 | 00000000000000000000000000000010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'acq_wrapper'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
WAIT_START | 00 | 00
|
|
WAIT_SAMPLE_ALIGN | 01 | 01
|
|
WAIT_CODE_PHASE | 10 | 10
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'current_state_reg' using encoding 'sequential' in module 'trck_cntrl'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
iSTATE0 | 0 | 00000000000000000000000000000000
|
|
*
|
|
iSTATE | 1 | 00000000000000000000000000000001
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'nav_solve_state_p_reg' using encoding 'sequential' in module 'nav_solve_timer'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
APB_STATE_IDLE | 001 | 00000000000000000000000000000000
|
|
APB_STATE_SEL | 010 | 00000000000000000000000000000001
|
|
APB_STATE_WR | 100 | 00000000000000000000000000000010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'apb_bus_ps_reg' using encoding 'one-hot' in module 'tracking_wrapper'
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:39 . Memory (MB): peak = 3017.984 ; gain = 1148.480 ; free physical = 6350 ; free virtual = 14957
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_1'
|
|
INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_2'
|
|
INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_3'
|
|
INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_4'
|
|
INFO: [Synth 8-223] decloning instance 'DTLB:/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'DTLB:/entries_barrier_5'
|
|
INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_1'
|
|
INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_2'
|
|
INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_3'
|
|
INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_4'
|
|
INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier' (OptimizationBarrier_TLBEntryData) to 'u_rocket/tile_prci_domain/element_reset_domain/rockettile/frontend/tlb/entries_barrier_5'
|
|
INFO: [Synth 8-223] decloning instance 'u_rocket/tile_prci_domain/intsource' (IntSyncCrossingSource_n1x1) to 'u_rocket/tile_prci_domain/intsource_2'
|
|
RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 109 Bit Adders := 1
|
|
2 Input 107 Bit Adders := 1
|
|
2 Input 66 Bit Adders := 1
|
|
3 Input 65 Bit Adders := 1
|
|
2 Input 64 Bit Adders := 7
|
|
3 Input 64 Bit Adders := 1
|
|
2 Input 62 Bit Adders := 1
|
|
3 Input 61 Bit Adders := 1
|
|
3 Input 58 Bit Adders := 1
|
|
2 Input 58 Bit Adders := 2
|
|
2 Input 55 Bit Adders := 4
|
|
2 Input 51 Bit Adders := 2
|
|
2 Input 49 Bit Adders := 1
|
|
2 Input 46 Bit Adders := 11
|
|
3 Input 46 Bit Adders := 2
|
|
2 Input 45 Bit Adders := 18
|
|
3 Input 45 Bit Adders := 10
|
|
2 Input 42 Bit Adders := 1
|
|
2 Input 41 Bit Adders := 9
|
|
3 Input 41 Bit Adders := 1
|
|
2 Input 34 Bit Adders := 3
|
|
3 Input 33 Bit Adders := 18
|
|
2 Input 32 Bit Adders := 75
|
|
3 Input 32 Bit Adders := 57
|
|
2 Input 30 Bit Adders := 18
|
|
3 Input 30 Bit Adders := 1
|
|
3 Input 29 Bit Adders := 1
|
|
2 Input 28 Bit Adders := 18
|
|
2 Input 26 Bit Adders := 25
|
|
3 Input 26 Bit Adders := 2
|
|
2 Input 25 Bit Adders := 11
|
|
3 Input 25 Bit Adders := 9
|
|
2 Input 23 Bit Adders := 54
|
|
2 Input 22 Bit Adders := 18
|
|
2 Input 18 Bit Adders := 2
|
|
3 Input 18 Bit Adders := 2
|
|
3 Input 16 Bit Adders := 1
|
|
2 Input 16 Bit Adders := 1
|
|
2 Input 15 Bit Adders := 2
|
|
2 Input 14 Bit Adders := 20
|
|
4 Input 14 Bit Adders := 1
|
|
3 Input 14 Bit Adders := 1
|
|
3 Input 13 Bit Adders := 2
|
|
2 Input 13 Bit Adders := 7
|
|
2 Input 12 Bit Adders := 13
|
|
3 Input 12 Bit Adders := 10
|
|
4 Input 11 Bit Adders := 1
|
|
2 Input 11 Bit Adders := 4
|
|
3 Input 10 Bit Adders := 2
|
|
2 Input 10 Bit Adders := 1
|
|
2 Input 9 Bit Adders := 11
|
|
3 Input 9 Bit Adders := 5
|
|
2 Input 8 Bit Adders := 5
|
|
2 Input 7 Bit Adders := 4
|
|
2 Input 6 Bit Adders := 24
|
|
3 Input 6 Bit Adders := 1
|
|
2 Input 5 Bit Adders := 41
|
|
2 Input 4 Bit Adders := 86
|
|
3 Input 4 Bit Adders := 1
|
|
3 Input 3 Bit Adders := 8
|
|
2 Input 3 Bit Adders := 32
|
|
2 Input 2 Bit Adders := 6
|
|
3 Input 2 Bit Adders := 4
|
|
4 Input 2 Bit Adders := 1
|
|
5 Input 2 Bit Adders := 1
|
|
3 Input 1 Bit Adders := 3
|
|
2 Input 1 Bit Adders := 41
|
|
+---XORs :
|
|
2 Input 65 Bit XORs := 1
|
|
2 Input 64 Bit XORs := 6
|
|
2 Input 33 Bit XORs := 1
|
|
2 Input 32 Bit XORs := 8
|
|
2 Input 29 Bit XORs := 16
|
|
2 Input 17 Bit XORs := 42
|
|
2 Input 16 Bit XORs := 1
|
|
2 Input 15 Bit XORs := 1
|
|
2 Input 14 Bit XORs := 4
|
|
2 Input 12 Bit XORs := 4
|
|
2 Input 10 Bit XORs := 4
|
|
2 Input 5 Bit XORs := 38
|
|
2 Input 4 Bit XORs := 2
|
|
2 Input 3 Bit XORs := 23
|
|
2 Input 2 Bit XORs := 7
|
|
2 Input 1 Bit XORs := 420
|
|
3 Input 1 Bit XORs := 68
|
|
6 Input 1 Bit XORs := 19
|
|
7 Input 1 Bit XORs := 18
|
|
13 Input 1 Bit XORs := 90
|
|
11 Input 1 Bit XORs := 63
|
|
12 Input 1 Bit XORs := 63
|
|
8 Input 1 Bit XORs := 54
|
|
10 Input 1 Bit XORs := 72
|
|
4 Input 1 Bit XORs := 54
|
|
14 Input 1 Bit XORs := 117
|
|
5 Input 1 Bit XORs := 18
|
|
15 Input 1 Bit XORs := 9
|
|
9 Input 1 Bit XORs := 54
|
|
16 Input 1 Bit XORs := 9
|
|
+---XORs :
|
|
5 Bit Wide XORs := 36
|
|
4 Bit Wide XORs := 36
|
|
3 Bit Wide XORs := 36
|
|
2 Bit Wide XORs := 36
|
|
+---Registers :
|
|
310 Bit Registers := 9
|
|
130 Bit Registers := 1
|
|
107 Bit Registers := 1
|
|
104 Bit Registers := 1
|
|
92 Bit Registers := 2
|
|
90 Bit Registers := 2
|
|
87 Bit Registers := 1
|
|
65 Bit Registers := 44
|
|
64 Bit Registers := 26
|
|
62 Bit Registers := 2
|
|
58 Bit Registers := 2
|
|
56 Bit Registers := 1
|
|
55 Bit Registers := 13
|
|
53 Bit Registers := 1
|
|
52 Bit Registers := 2
|
|
51 Bit Registers := 8
|
|
50 Bit Registers := 9
|
|
49 Bit Registers := 2
|
|
48 Bit Registers := 77
|
|
46 Bit Registers := 9
|
|
45 Bit Registers := 2
|
|
43 Bit Registers := 1
|
|
41 Bit Registers := 11
|
|
40 Bit Registers := 9
|
|
36 Bit Registers := 3
|
|
34 Bit Registers := 25
|
|
33 Bit Registers := 30
|
|
32 Bit Registers := 204
|
|
31 Bit Registers := 90
|
|
30 Bit Registers := 28
|
|
29 Bit Registers := 5
|
|
28 Bit Registers := 20
|
|
27 Bit Registers := 1
|
|
26 Bit Registers := 22
|
|
24 Bit Registers := 40
|
|
22 Bit Registers := 136
|
|
21 Bit Registers := 9
|
|
20 Bit Registers := 2
|
|
18 Bit Registers := 9
|
|
17 Bit Registers := 3
|
|
16 Bit Registers := 18
|
|
15 Bit Registers := 53
|
|
14 Bit Registers := 50
|
|
13 Bit Registers := 9
|
|
12 Bit Registers := 21
|
|
10 Bit Registers := 30
|
|
9 Bit Registers := 13
|
|
8 Bit Registers := 112
|
|
7 Bit Registers := 12
|
|
6 Bit Registers := 82
|
|
5 Bit Registers := 106
|
|
4 Bit Registers := 215
|
|
3 Bit Registers := 148
|
|
2 Bit Registers := 214
|
|
1 Bit Registers := 1405
|
|
+---Multipliers :
|
|
53x53 Multipliers := 1
|
|
66x66 Multipliers := 1
|
|
15x46 Multipliers := 4
|
|
25x30 Multipliers := 9
|
|
+---RAMs :
|
|
8192K Bit (131072 X 64 bit) RAMs := 1
|
|
1472K Bit (16384 X 92 bit) RAMs := 1
|
|
832K Bit (16384 X 52 bit) RAMs := 1
|
|
816K Bit (16384 X 51 bit) RAMs := 1
|
|
768K Bit (16384 X 48 bit) RAMs := 1
|
|
576K Bit (16384 X 36 bit) RAMs := 1
|
|
128K Bit (32768 X 4 bit) RAMs := 1
|
|
16K Bit (512 X 32 bit) RAMs := 2
|
|
1K Bit (64 X 21 bit) RAMs := 1
|
|
+---ROMs :
|
|
ROMs := 6
|
|
+---Muxes :
|
|
2 Input 2080 Bit Muxes := 1
|
|
2 Input 130 Bit Muxes := 3
|
|
2 Input 109 Bit Muxes := 1
|
|
2 Input 108 Bit Muxes := 1
|
|
2 Input 92 Bit Muxes := 6
|
|
2 Input 65 Bit Muxes := 18
|
|
4 Input 65 Bit Muxes := 1
|
|
2 Input 64 Bit Muxes := 118
|
|
4 Input 64 Bit Muxes := 7
|
|
2 Input 62 Bit Muxes := 1
|
|
2 Input 61 Bit Muxes := 2
|
|
2 Input 58 Bit Muxes := 2
|
|
2 Input 56 Bit Muxes := 5
|
|
2 Input 55 Bit Muxes := 11
|
|
2 Input 54 Bit Muxes := 3
|
|
2 Input 53 Bit Muxes := 2
|
|
2 Input 52 Bit Muxes := 16
|
|
2 Input 51 Bit Muxes := 5
|
|
2 Input 50 Bit Muxes := 10
|
|
2 Input 48 Bit Muxes := 3
|
|
2 Input 46 Bit Muxes := 27
|
|
2 Input 45 Bit Muxes := 21
|
|
3 Input 45 Bit Muxes := 2
|
|
2 Input 44 Bit Muxes := 4
|
|
2 Input 41 Bit Muxes := 7
|
|
2 Input 36 Bit Muxes := 6
|
|
7 Input 36 Bit Muxes := 1
|
|
2 Input 34 Bit Muxes := 30
|
|
2 Input 33 Bit Muxes := 39
|
|
2 Input 32 Bit Muxes := 318
|
|
3 Input 32 Bit Muxes := 1
|
|
4 Input 32 Bit Muxes := 1
|
|
2 Input 30 Bit Muxes := 9
|
|
2 Input 29 Bit Muxes := 8
|
|
2 Input 28 Bit Muxes := 1
|
|
2 Input 27 Bit Muxes := 4
|
|
2 Input 26 Bit Muxes := 15
|
|
2 Input 25 Bit Muxes := 25
|
|
2 Input 24 Bit Muxes := 97
|
|
2 Input 23 Bit Muxes := 65
|
|
2 Input 22 Bit Muxes := 78
|
|
2 Input 20 Bit Muxes := 4
|
|
2 Input 17 Bit Muxes := 1
|
|
2 Input 16 Bit Muxes := 13
|
|
3 Input 16 Bit Muxes := 1
|
|
7 Input 16 Bit Muxes := 1
|
|
2 Input 15 Bit Muxes := 18
|
|
2 Input 14 Bit Muxes := 62
|
|
7 Input 14 Bit Muxes := 1
|
|
2 Input 13 Bit Muxes := 20
|
|
2 Input 12 Bit Muxes := 51
|
|
2 Input 11 Bit Muxes := 2
|
|
2 Input 10 Bit Muxes := 13
|
|
2 Input 9 Bit Muxes := 34
|
|
3 Input 9 Bit Muxes := 1
|
|
2 Input 8 Bit Muxes := 208
|
|
8 Input 8 Bit Muxes := 18
|
|
2 Input 7 Bit Muxes := 20
|
|
7 Input 7 Bit Muxes := 1
|
|
4 Input 6 Bit Muxes := 1
|
|
2 Input 6 Bit Muxes := 63
|
|
3 Input 6 Bit Muxes := 2
|
|
7 Input 6 Bit Muxes := 3
|
|
2 Input 5 Bit Muxes := 58
|
|
4 Input 5 Bit Muxes := 1
|
|
5 Input 5 Bit Muxes := 2
|
|
3 Input 5 Bit Muxes := 2
|
|
2 Input 4 Bit Muxes := 118
|
|
4 Input 4 Bit Muxes := 3
|
|
8 Input 4 Bit Muxes := 1
|
|
3 Input 4 Bit Muxes := 1
|
|
7 Input 4 Bit Muxes := 2
|
|
2 Input 3 Bit Muxes := 167
|
|
6 Input 3 Bit Muxes := 3
|
|
8 Input 3 Bit Muxes := 3
|
|
4 Input 3 Bit Muxes := 3
|
|
3 Input 3 Bit Muxes := 28
|
|
7 Input 3 Bit Muxes := 1
|
|
5 Input 3 Bit Muxes := 2
|
|
2 Input 2 Bit Muxes := 154
|
|
16 Input 2 Bit Muxes := 1
|
|
3 Input 2 Bit Muxes := 13
|
|
4 Input 2 Bit Muxes := 5
|
|
7 Input 2 Bit Muxes := 1
|
|
8 Input 2 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 1354
|
|
3 Input 1 Bit Muxes := 41
|
|
5 Input 1 Bit Muxes := 27
|
|
4 Input 1 Bit Muxes := 21
|
|
6 Input 1 Bit Muxes := 1
|
|
7 Input 1 Bit Muxes := 9
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 840 (col length:140)
|
|
BRAMs: 890 (col length: RAMB18 140 RAMB36 70)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 10. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/MulAddRecFNPipe_l2_e11_s53.sv:136]
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: PCIN+A*B.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: A*B.
|
|
DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: Generating DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
DSP Report: operator mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1 is absorbed into DSP mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1.
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (dfma/\io_out_pipe_b_exc_reg[3] )
|
|
INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_vec_reg' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
|
|
INFO: [Synth 8-3886] merging instance 'mem_ctrl_vec_reg' (FDE) to 'mem_ctrl_typeTagOut_reg[1]'
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\io_out_pipe_b_exc_reg[3] )
|
|
INFO: [Synth 8-3886] merging instance 'ex_reg_ctrl_typeTagIn_reg[1]' (FDE) to 'ex_reg_ctrl_typeTagOut_reg[1]'
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\ex_reg_ctrl_typeTagOut_reg[1] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (fpmu/\in_pipe_b_typeTagOut_reg[1] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\mem_ctrl_typeTagOut_reg[1] )
|
|
INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[1]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[2]'
|
|
INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[2]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[3]'
|
|
INFO: [Synth 8-3886] merging instance 'ifpu/io_out_pipe_b_exc_reg[3]' (FDE) to 'ifpu/io_out_pipe_b_exc_reg[4]'
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (ifpu/\io_out_pipe_b_exc_reg[4] )
|
|
INFO: [Synth 8-4471] merging register 's2_tlb_resp_pf_inst_reg' into 's2_tlb_resp_cacheable_reg' [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/Frontend.sv:127]
|
|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 16. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/MulDiv.sv:131]
|
|
DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: PCIN+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: Generating DSP remainder1, operation Mode is: (PCIN>>17)+A2*B2.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: register remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
DSP Report: operator remainder1 is absorbed into DSP remainder1.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_tag_array_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[60]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[60]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[61]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[61]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[62]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[62]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[57]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[57]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[58]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[58]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[59]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[59]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[54]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[54]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[55]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[55]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[56]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[56]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[51]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[51]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[52]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[52]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[53]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[53]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[48]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[48]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[49]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[49]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[50]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[50]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[45]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[45]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[46]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[46]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[47]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[47]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[42]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[42]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[43]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[43]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[44]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[44]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[39]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[39]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[40]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[40]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[41]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[41]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[36]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[36]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[37]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[37]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[38]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[38]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[33]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[33]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[34]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[34]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[35]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[35]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[30]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[30]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[31]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[31]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[32]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[32]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[27]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[27]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[28]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[28]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[29]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[29]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[24]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[24]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[25]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[25]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[26]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[26]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[21]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[21]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[22]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[22]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[23]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[23]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[18]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[18]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[19]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[19]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[20]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[20]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[15]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[15]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/ex_reg_cause_reg[16]' (FDE) to 'core/ex_reg_cause_reg[5]'
|
|
INFO: [Synth 8-3886] merging instance 'core/mem_reg_cause_reg[16]' (FDE) to 'core/mem_reg_cause_reg[5]'
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_reg_cause_reg[5] )
|
|
INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_mstatus_mpp_reg[1] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mcountinhibit_reg[1] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_mie_reg[0] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/\s1_pc_reg[0] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_mem_cmd_reg[4] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/\ex_ctrl_sel_alu2_reg[2] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (frontend/s2_tlb_resp_cacheable_reg)
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[32] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[32] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[2] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[4] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[4] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[5] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[6] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[6] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[7] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[7] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[8] )
|
|
INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[8] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[9] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[9] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[10] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[10] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[11] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[11] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[12] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[13] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[13] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[14] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[14] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[15] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[15] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[16] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[16] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[17] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[17] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[18] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[18] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[19] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[19] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[20] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[20] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[21] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[21] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[22] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[22] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[23] )
|
|
INFO: [Synth 8-3333] propagating constant 1 across sequential element (core/csr/\reg_misa_reg[23] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[24] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[24] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[25] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[25] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[26] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[26] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[27] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[27] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[28] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[28] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[29] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[29] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[30] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[30] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[31] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[31] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[33] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[33] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[34] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[34] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[35] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[35] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[36] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[36] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[37] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[37] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[38] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[38] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[39] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[39] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[40] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[40] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[41] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[41] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[42] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[42] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[43] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[43] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[44] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[44] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[45] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[45] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[46] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_misa_reg[46] )
|
|
INFO: [Synth 8-3333] propagating constant 0 across sequential element (core/csr/\reg_custom_0_reg[47] )
|
|
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Common 17-14] Message 'Synth 8-3333' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
WARNING: [Synth 8-3936] Found unconnected internal register 's2_req_addr_reg' and it is trimmed from '34' to '32' bits. [/home/onur/Desktop/tmp/rocket-chip/hardware/generated/genesys2-soc-verilog/DCache.sv:408]
|
|
WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[3] driven by constant 0
|
|
WARNING: [Synth 8-3917] design DCache has port auto_out_a_bits_size[2] driven by constant 0
|
|
RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
WARNING: [Synth 8-6841] Block RAM (rockettile_dcache_data_arrays_0_ext/Memory_reg) originally specified as a Byte Wide Write Enable RAM cannot take advantage of ByteWide feature and is implemented with single write enable per RAM due to following reason.
|
|
(address width (17) is more than optimal threshold of 12. Implementing using BWWE will require more logic and timing would be suboptimal. Please use attribute ram_decomp = power if BWWE is desired.)
|
|
RAM Pipeline Warning: Read Address Register Found For RAM rockettile_dcache_data_arrays_0_ext/Memory_reg. We will not be able to pipeline it. This may degrade performance.
|
|
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
|
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 1. Recommended levels of pipeline registers is 4. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:129]
|
|
DSP Report: Generating DSP freq_word0, operation Mode is: (A:0x6677)*B.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: Generating DSP freq_word0, operation Mode is: A*(B:0x6677).
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: Generating DSP freq_word0, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: operator freq_word0 is absorbed into DSP freq_word0.
|
|
DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x109).
|
|
DSP Report: operator mult10 is absorbed into DSP mult10.
|
|
DSP Report: Generating DSP mult10, operation Mode is: A*(B:0x55).
|
|
DSP Report: operator mult10 is absorbed into DSP mult10.
|
|
DSP Report: Generating DSP mult20, operation Mode is: A*(B:0x75).
|
|
DSP Report: operator mult20 is absorbed into DSP mult20.
|
|
INFO: [Synth 8-5544] ROM "cordic_angle_lut_i/angle_o" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
|
|
INFO: [Synth 8-4471] merging register 'prompt_abs_vld_reg' into 'cos2x_i/sqr_vld_reg' [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:105]
|
|
DSP Report: Generating DSP cos2x_i/q_p_sqr0, operation Mode is: A*B.
|
|
DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
|
|
DSP Report: operator cos2x_i/q_p_sqr0 is absorbed into DSP cos2x_i/q_p_sqr0.
|
|
DSP Report: Generating DSP cos2x_i/i_p_sqr0, operation Mode is: A*B.
|
|
DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
|
|
DSP Report: operator cos2x_i/i_p_sqr0 is absorbed into DSP cos2x_i/i_p_sqr0.
|
|
DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: A*B.
|
|
DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
|
|
DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
|
|
DSP Report: Generating DSP q_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
|
|
DSP Report: operator q_prompt_energy_r0 is absorbed into DSP q_prompt_energy_r0.
|
|
DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: A*B.
|
|
DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
|
|
DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
|
|
DSP Report: Generating DSP i_prompt_energy_r0, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
|
|
DSP Report: operator i_prompt_energy_r0 is absorbed into DSP i_prompt_energy_r0.
|
|
INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
|
|
INFO: [Synth 8-5546] ROM "control_reg_n" won't be mapped to RAM because it is too sparse
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__0) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[47]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[46]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[45]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[44]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[43]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[42]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[41]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[40]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[39]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[38]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[37]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[36]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[35]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[34]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[33]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[32]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[31]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[30]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[29]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[28]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[27]__1) is unused and will be removed from module NCO_carr.
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WARNING: [Synth 8-3332] Sequential element (freq_word_reg[26]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[25]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[24]__1) is unused and will be removed from module NCO_carr.
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|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[23]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[22]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[21]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[20]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[19]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[18]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[17]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[15]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[14]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[13]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[12]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[11]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[10]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[9]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[8]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[7]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[6]__1) is unused and will be removed from module NCO_carr.
|
|
WARNING: [Synth 8-3332] Sequential element (freq_word_reg[5]__1) is unused and will be removed from module NCO_carr.
|
|
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Common 17-14] Message 'Synth 8-3332' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
|
INFO: [Synth 8-5542] Attribute ram_style/rom_style = distributed specified for ROM "p_0_out". This will be implemented in logic
|
|
DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: Generating DSP p_1_out, operation Mode is: (C or 0)+A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP p_1_out.
|
|
DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
|
|
DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
|
|
DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
|
|
DSP Report: Generating DSP k0, operation Mode is: A*B.
|
|
DSP Report: operator k0 is absorbed into DSP k0.
|
|
DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
|
|
DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
|
|
DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w0, operation Mode is: C+A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w0 is absorbed into DSP butterfly_i/x1_imag_w0.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w0.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w0, operation Mode is: C-A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w0 is absorbed into DSP butterfly_i/x1_real_w0.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w0.
|
|
DSP Report: Generating DSP k0, operation Mode is: A*B.
|
|
DSP Report: operator k0 is absorbed into DSP k0.
|
|
DSP Report: Generating DSP bd, operation Mode is: A*B.
|
|
DSP Report: operator bd is absorbed into DSP bd.
|
|
DSP Report: Generating DSP ac, operation Mode is: A*B.
|
|
DSP Report: operator ac is absorbed into DSP ac.
|
|
DSP Report: Generating DSP ad, operation Mode is: A*B.
|
|
DSP Report: operator ad is absorbed into DSP ad.
|
|
DSP Report: Generating DSP bc, operation Mode is: A*B.
|
|
DSP Report: operator bc is absorbed into DSP bc.
|
|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
|
|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:44]
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|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
|
|
INFO: [Synth 8-12192] Not enough pipeline registers after wide multiplier. Pipeline registers present is 0. Recommended levels of pipeline registers is 3. [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/butterfly.sv:43]
|
|
DSP Report: Generating DSP port1_addr0, operation Mode is: C+A*B.
|
|
DSP Report: operator port1_addr0 is absorbed into DSP port1_addr0.
|
|
DSP Report: operator port1_addr1 is absorbed into DSP port1_addr0.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_imag_w1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: operator butterfly_i/x1_imag_w1 is absorbed into DSP butterfly_i/x1_imag_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP butterfly_i/x1_real_w1, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: operator butterfly_i/x1_real_w1 is absorbed into DSP butterfly_i/x1_real_w1.
|
|
DSP Report: Generating DSP k0, operation Mode is: A*B.
|
|
DSP Report: operator k0 is absorbed into DSP k0.
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DSP Report: Generating DSP im_sqr0, operation Mode is: A*B.
|
|
DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
|
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DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
|
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DSP Report: Generating DSP im_sqr0, operation Mode is: (PCIN>>17)+A*B.
|
|
DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
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DSP Report: operator im_sqr0 is absorbed into DSP im_sqr0.
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DSP Report: Generating DSP re_sqr0, operation Mode is: A*B.
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DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
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DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
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DSP Report: Generating DSP re_sqr0, operation Mode is: (PCIN>>17)+A*B.
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DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
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DSP Report: operator re_sqr0 is absorbed into DSP re_sqr0.
|
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INFO: [Synth 8-4652] Swapped enable and write-enable on 4 RAM instances of RAM acq/i_acq_top/dual_port_ram_i/ram_reg to conserve power
|
|
INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_IQ_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
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INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /fft_code_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
|
|
INFO: [Synth 8-3971] The signal "\acq/i_acq_top/acq_corr_inst /ifft_inst/dual_port_bram_i/ram_reg" was recognized as a true dual port RAM template.
|
|
INFO: [Synth 8-4652] Swapped enable and write-enable on 26 RAM instances of RAM bram_i/ram_reg to conserve power
|
|
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_60_65 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_54_59 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_48_53 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_42_47 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_36_41 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_30_35 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_24_29 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_18_23 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Synth 8-7067] Removed DRAM instance cbus/wrapped_error_device/i_1/buffer/nodeIn_d_q/ram_ext/Memory_reg_0_1_66_71 from module ErrorDeviceWrapper due to constant propagation
|
|
INFO: [Common 17-14] Message 'Synth 8-3886' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:19 ; elapsed = 00:01:38 . Memory (MB): peak = 3033.996 ; gain = 1164.492 ; free physical = 2738 ; free virtual = 11853
|
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---------------------------------------------------------------------------------
|
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Sort Area is APBGpsBlock__GC0 p_1_out_0 : 0 0 : 2790 2790 : Used 1 time 100
|
|
Sort Area is APBGpsBlock__GC0 p_1_out_2 : 0 0 : 2790 2790 : Used 1 time 100
|
|
Sort Area is APBGpsBlock__GC0 p_1_out_3 : 0 0 : 2790 2790 : Used 1 time 100
|
|
Sort Area is APBGpsBlock__GC0 p_1_out_4 : 0 0 : 2790 2790 : Used 1 time 100
|
|
Sort Area is RocketTile__GCB0 remainder1_0 : 0 0 : 3137 12586 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_0 : 0 1 : 3156 12586 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_0 : 0 2 : 3137 12586 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_0 : 0 3 : 3156 12586 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_4 : 0 0 : 3137 12223 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_4 : 0 1 : 3137 12223 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_4 : 0 2 : 2812 12223 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_4 : 0 3 : 3137 12223 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_6 : 0 0 : 3137 11879 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_6 : 0 1 : 2793 11879 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_6 : 0 2 : 2812 11879 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_6 : 0 3 : 3137 11879 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_8 : 0 0 : 2793 11089 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_8 : 0 1 : 2812 11089 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_8 : 0 2 : 2793 11089 : Used 1 time 0
|
|
Sort Area is RocketTile__GCB0 remainder1_8 : 0 3 : 2691 11089 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 0 : 3236 9727 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 1 : 3236 9727 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_7 : 0 2 : 3255 9727 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 0 : 3236 9573 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 1 : 3101 9573 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_4 : 0 2 : 3236 9573 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 0 : 3101 9322 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 1 : 3120 9322 : Used 1 time 0
|
|
Sort Area is FPU__GB1 fma/mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_0 : 0 2 : 3101 9322 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 im_sqr0_26 : 0 0 : 3406 4775 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 im_sqr0_26 : 0 1 : 1369 4775 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 re_sqr0_23 : 0 0 : 3406 4775 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 re_sqr0_23 : 0 1 : 1369 4775 : Used 1 time 0
|
|
Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 0 : 3446 4760 : Used 1 time 0
|
|
Sort Area is FPU__GB1 mulAddRecFNToRaw_postMul_io_mulAddResult_pipe_b1_9 : 0 1 : 1314 4760 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_1e : 0 0 : 1981 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_1e : 0 1 : 2653 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_20 : 0 0 : 1981 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_20 : 0 1 : 2653 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_18 : 0 0 : 1981 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_18 : 0 1 : 2653 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1c : 0 0 : 1981 4634 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1c : 0 1 : 2653 4634 : Used 1 time 0
|
|
Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 0 : 3234 4210 : Used 9 time 0
|
|
Sort Area is tracking_wrapper i_prompt_energy_r0_e : 0 1 : 976 4210 : Used 9 time 0
|
|
Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 0 : 3234 4210 : Used 9 time 0
|
|
Sort Area is tracking_wrapper q_prompt_energy_r0_11 : 0 1 : 976 4210 : Used 9 time 0
|
|
Sort Area is tracking_wrapper freq_word0_0 : 0 0 : 1789 3431 : Used 9 time 0
|
|
Sort Area is tracking_wrapper freq_word0_0 : 0 1 : 1642 3431 : Used 9 time 0
|
|
Sort Area is tracking_wrapper freq_word0_3 : 0 0 : 1785 3295 : Used 9 time 0
|
|
Sort Area is tracking_wrapper freq_word0_3 : 0 1 : 1510 3295 : Used 9 time 0
|
|
Sort Area is tracking_wrapper cos2x_i/i_p_sqr0_b : 0 0 : 3088 3088 : Used 9 time 0
|
|
Sort Area is tracking_wrapper cos2x_i/q_p_sqr0_d : 0 0 : 3088 3088 : Used 9 time 0
|
|
Sort Area is APBGpsBlock__GC0 ac_12 : 0 0 : 2310 2310 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 ad_16 : 0 0 : 2310 2310 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 bc_15 : 0 0 : 2310 2310 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 bd_14 : 0 0 : 2310 2310 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w0_c : 0 0 : 2196 2196 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w0_f : 0 0 : 2073 2073 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_e : 0 0 : 1981 1981 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_a : 0 0 : 1981 1981 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_1f : 0 0 : 1954 1954 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_imag_w1_21 : 0 0 : 1954 1954 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1a : 0 0 : 1954 1954 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 butterfly_i/x1_real_w1_1d : 0 0 : 1954 1954 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 port1_addr0_17 : 0 0 : 1357 1357 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 port1_addr0_5 : 0 0 : 1357 1357 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 port1_addr0_9 : 0 0 : 1357 1357 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 k0_11 : 0 0 : 1238 1238 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 k0_22 : 0 0 : 1238 1238 : Used 1 time 0
|
|
Sort Area is APBGpsBlock__GC0 k0_7 : 0 0 : 1238 1238 : Used 1 time 0
|
|
Sort Area is tracking_wrapper mult10_6 : 0 0 : 433 433 : Used 9 time 0
|
|
Sort Area is tracking_wrapper mult10_a : 0 0 : 403 403 : Used 9 time 0
|
|
Sort Area is tracking_wrapper mult20_8 : 0 0 : 403 403 : Used 9 time 0
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
ROM: Preliminary Mapping Report
|
|
+----------------+----------------------+---------------+----------------+
|
|
|Module Name | RTL Object | Depth x Width | Implemented As |
|
|
+----------------+----------------------+---------------+----------------+
|
|
|TLROM | _GEN | 256x64 | LUT |
|
|
|acq_nco_carr | freq_word_arr | 64x13 | LUT |
|
|
|acq_nco_carr | pullin_freq_word_arr | 16x11 | LUT |
|
|
|acq_nco_carr | sinwav_lut | 32x6 | LUT |
|
|
|acq_nco_carr | sinwav_lut | 32x6 | LUT |
|
|
|acq_ca_gen | p_0_out | 32x8 | LUT |
|
|
|NCO_carr | sinwav_lut | 128x6 | LUT |
|
|
|NCO_carr | sinwav_lut | 128x6 | LUT |
|
|
|cacode_gen_trck | p_0_out | 32x8 | LUT |
|
|
+----------------+----------------------+---------------+----------------+
|
|
|
|
|
|
Block RAM: Preliminary Mapping Report (see note below)
|
|
+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
|
+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
|
|
|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|
|
|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|
|
|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|
|
|APBGpsBlock__GC0 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
|
|
|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
|
|
|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
|
|
|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
|
|
|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
|
|
|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
|
|
+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|
|
Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once.
|
|
|
|
Distributed RAM: Preliminary Mapping Report (see note below)
|
|
+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
|
|
|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
|
|
+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
|
|
|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
|
|
|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
|
|
|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
|
|
|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
|
|
|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
|
|
|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
|
|
|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
|
|
|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
|
|
|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
|
|
|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
|
|
|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
|
|
|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
|
|
|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
|
|
|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
|
|
|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
|
|
|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
|
|
+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
|
|
|
|
Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
|
|
|
|
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
|
|
+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
|
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
|
|
+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
|
|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A*B | 20 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | (PCIN>>17)+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A*B | 18 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|MulAddRecFNPipe_l2_e8_s24 | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|MulAddRecFNPipe_l2_e8_s24 | (PCIN>>17)+A*B | 25 | 8 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|MulDiv | A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | (PCIN>>17)+A2*B2 | 16 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | (PCIN>>17)+A2*B2 | 18 | 16 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | (PCIN>>17)+A2*B2 | 18 | 18 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (A:0x6677)*B | 14 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17)+A*B | 14 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | A*(B:0x6677) | 18 | 16 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17)+A*B | 18 | 9 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | A*(B:0x109) | 12 | 10 | - | - | 22 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_code | A*(B:0x55) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_code | A*(B:0x75) | 15 | 8 | - | - | 23 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 22 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | A*B | 23 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17)+A*B | 23 | 6 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|butterfly | (C or 0)+A*B | 25 | 15 | 14 | - | 40 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | C+A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|butterfly | A*B | 18 | 15 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | C-A*B | 18 | 15 | 31 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 20 | 16 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 15 | 12 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | (PCIN>>17)+A*B | 18 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | A*B | 25 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | (PCIN>>17)+A*B | 25 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
+--------------------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
|
|
|
Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:00 ; elapsed = 00:01:46 . Memory (MB): peak = 3033.996 ; gain = 1164.492 ; free physical = 5460 ; free virtual = 14671
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:03:08 ; elapsed = 00:01:55 . Memory (MB): peak = 3050.105 ; gain = 1180.602 ; free physical = 4887 ; free virtual = 14146
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
Block RAM: Final Mapping Report
|
|
+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|Module Name | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 |
|
|
+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|
|
|data | rockettile_dcache_data_arrays_0_ext/Memory_reg | 128 K x 64(WRITE_FIRST) | W | R | | | | Port A | 0 | 256 |
|
|
|frontend | icache/rockettile_icache_tag_array_0_ext/Memory_reg | 64 x 21(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|
|
|frontend | icache/rockettile_icache_data_arrays_0_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|
|
|frontend | icache/rockettile_icache_data_arrays_1_0_ext/Memory_reg | 512 x 32(WRITE_FIRST) | W | R | | | | Port A | 1 | 0 |
|
|
|APBGpsBlock__GC0 | acq/i_acq_top/dual_port_ram_i/ram_reg | 32 K x 4(NO_CHANGE) | W | | 32 K x 4(WRITE_FIRST) | | R | Port A and B | 0 | 4 |
|
|
|\acq/i_acq_top/acq_corr_inst /fft_IQ_inst | dual_port_bram_i/ram_reg | 16 K x 52(READ_FIRST) | W | R | 16 K x 52(READ_FIRST) | W | R | Port A and B | 0 | 26 |
|
|
|\acq/i_acq_top/acq_corr_inst /fft_code_inst | dual_port_bram_i/ram_reg | 16 K x 36(READ_FIRST) | W | R | 16 K x 36(READ_FIRST) | W | R | Port A and B | 0 | 18 |
|
|
|\acq/i_acq_top/acq_corr_inst /ifft_inst | dual_port_bram_i/ram_reg | 16 K x 92(READ_FIRST) | W | R | 16 K x 92(READ_FIRST) | W | R | Port A and B | 0 | 46 |
|
|
|\acq/i_acq_top/acq_corr_inst | coh_ram_inst/ram_reg | 16 K x 48(READ_FIRST) | W | R | | | | Port A | 0 | 24 |
|
|
|\acq/i_acq_top/acq_corr_inst /acq_peak_srch_inst | bram_i/ram_reg | 16 K x 51(READ_FIRST) | W | | 16 K x 51(WRITE_FIRST) | | R | Port A and B | 1 | 25 |
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+-------------------------------------------------+---------------------------------------------------------+-------------------------+---+---+------------------------+---+---+------------------+--------+--------+
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Distributed RAM: Final Mapping Report
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+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
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|Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives |
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+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
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|core | rf_ext/Memory_reg | Implied | 32 x 64 | RAM32M x 22 |
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|u_rocket | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
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|u_rocket | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
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|u_rocket | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 115 | RAM32M x 20 |
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|u_rocket | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
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|pbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
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|pbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
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|pbus | buffer_1/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 120 | RAM32M x 20 |
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|pbus | buffer_1/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
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|fbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 123 | RAM32M x 21 |
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|fbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 77 | RAM32M x 13 |
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|cbus | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 124 | RAM32M x 21 |
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|cbus | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
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|cbus/wrapped_error_device | buffer/nodeOut_a_q/ram_ext/Memory_reg | Implied | 2 x 99 | RAM32M x 17 |
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|cbus/wrapped_error_device | buffer/nodeIn_d_q/ram_ext/Memory_reg | Implied | 2 x 78 | RAM32M x 13 |
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|tlDM/\dmInner/dmInner /sb2tlOpt | d_q/ram_ext/Memory_reg | Implied | 2 x 10 | RAM32M x 2 |
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+--------------------------------+-----------------------------------------+-----------+----------------------+--------------+
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---------------------------------------------------------------------------------
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Technology Mapping
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---------------------------------------------------------------------------------
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_0_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_1_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_2_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_3_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_4_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_1_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_4 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_5 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_6 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_5_3_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_0 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_1 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_2 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Synth 8-7052] The timing for the instance u_rocket/tile_prci_domain/element_reset_domain/rockettile/dcache/data/rockettile_dcache_data_arrays_0_ext/Memory_reg_6_1_3 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
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INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/NCO_carr.sv:127]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/LF_carr.sv:48]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:61]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/LF_code.sv:74]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:104]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:103]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:130]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:130]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:130]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/trck_top.sv:130]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/cordic_atan_basic.sv:100]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/divider.sv:48]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:95]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/accum_dump.sv:92]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:102]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:102]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:102]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:102]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:101]
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|
INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:101]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:101]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/trck_src/lock_detector.sv:101]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:78]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/ifft_abs_sqr.sv:79]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:301]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
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INFO: [Synth 8-5844] Detected registers with asynchronous reset at DSP/BRAM block boundary. Consider using synchronous reset for optimal packing [/home/onur/Desktop/tmp/rocket-chip/hardware/external/gps/rtl/acq_src/fft_radix_2.sv:302]
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INFO: [Common 17-14] Message 'Synth 8-7052' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
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---------------------------------------------------------------------------------
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Finished Technology Mapping : Time (s): cpu = 00:03:16 ; elapsed = 00:02:07 . Memory (MB): peak = 3070.039 ; gain = 1200.535 ; free physical = 3359 ; free virtual = 12639
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Final Netlist Cleanup
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished IO Insertion : Time (s): cpu = 00:03:24 ; elapsed = 00:02:16 . Memory (MB): peak = 3225.938 ; gain = 1356.434 ; free physical = 3128 ; free virtual = 12458
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Instances
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Instances : Time (s): cpu = 00:03:24 ; elapsed = 00:02:16 . Memory (MB): peak = 3225.938 ; gain = 1356.434 ; free physical = 3128 ; free virtual = 12458
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Rebuilding User Hierarchy
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:35 ; elapsed = 00:02:27 . Memory (MB): peak = 3396.445 ; gain = 1526.941 ; free physical = 2976 ; free virtual = 12320
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Ports
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Ports : Time (s): cpu = 00:03:35 ; elapsed = 00:02:27 . Memory (MB): peak = 3396.445 ; gain = 1526.941 ; free physical = 2978 ; free virtual = 12323
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Handling Custom Attributes
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Handling Custom Attributes : Time (s): cpu = 00:03:36 ; elapsed = 00:02:28 . Memory (MB): peak = 3411.289 ; gain = 1541.785 ; free physical = 2982 ; free virtual = 12329
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Renaming Generated Nets
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Finished Renaming Generated Nets : Time (s): cpu = 00:03:36 ; elapsed = 00:02:29 . Memory (MB): peak = 3411.289 ; gain = 1541.785 ; free physical = 2982 ; free virtual = 12329
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting
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---------------------------------------------------------------------------------
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Static Shift Register Report:
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+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
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|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
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+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|
|
|VCU118RocketSystem | tile_prci_domain/intsink/chain/output_chain/sync_0_reg | 3 | 1 | NO | NO | YES | 1 | 0 |
|
|
+-------------------+--------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|
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|
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---------------------------------------------------------------------------------
|
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Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
|
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Start Writing Synthesis Report
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---------------------------------------------------------------------------------
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|
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DSP Final Report (the ' indicates corresponding REG is set)
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+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
|
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
|
|
+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
|
|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|comp_mult | A*B | 30 | 18 | - | - | 36 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
|
|
|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
|
|
|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
|
|
|butterfly | Dynamic | - | - | - | - | 40 | - | - | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | C+A*B | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|butterfly | A*B | 30 | 18 | - | - | 33 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|butterfly | C-(A*B) | 30 | 18 | 48 | - | 31 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|ifft_abs_sqr | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|ifft_abs_sqr | (PCIN>>17+A*B)' | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|fft_radix_2 | C+A*B | 14 | 13 | 13 | - | 14 | 0 | 0 | 0 | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 13 | 13 | - | - | 26 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 30 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|fft_radix_2 | PCIN>>17+A*B | 17 | 18 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
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|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
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|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
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|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
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|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
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|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
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|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
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|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
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|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
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|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
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|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|LF_carr | (A*B)' | 30 | 9 | - | - | 22 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|LF_code | (A*B)' | 30 | 7 | - | - | 23 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 13 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|NCO_carr | A*B | 17 | 15 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|NCO_carr | (PCIN>>17+A*B)' | 0 | 8 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|lock_detector | A*B | 22 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|lock_detector | (PCIN>>17+A*B)' | 22 | 5 | - | - | 48 | 0 | 0 | - | - | - | 0 | 1 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|cos2x | A*B | 30 | 17 | - | - | 48 | 0 | 0 | - | - | - | 0 | 0 |
|
|
|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A'*B' | 17 | 15 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN>>17+A'*B' | 17 | 15 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 0 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulDiv | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN>>17+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A*B' | 19 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN>>17+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|FPUFMAPipe_l4_f64 | PCIN+A'*B' | 17 | 17 | - | - | 48 | 1 | 1 | - | - | - | 0 | 0 |
|
|
|MulAddRecFNPipe_l2_e8_s24 | A*B' | 24 | 17 | - | - | 48 | 0 | 1 | - | - | - | 0 | 0 |
|
|
|MulAddRecFNPipe_l2_e8_s24 | PCIN>>17+A*B | 24 | 7 | - | - | 31 | 0 | 0 | - | - | - | 0 | 0 |
|
|
+--------------------------+-----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|
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|
|
Report BlackBoxes:
|
|
+-+--------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+-+--------------+----------+
|
|
+-+--------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+-----------+------+
|
|
| |Cell |Count |
|
|
+------+-----------+------+
|
|
|1 |BSCANE2 | 1|
|
|
|2 |BUFG | 6|
|
|
|3 |CARRY4 | 5424|
|
|
|4 |DSP48E1 | 172|
|
|
|10 |LUT1 | 2670|
|
|
|11 |LUT2 | 13389|
|
|
|12 |LUT3 | 9895|
|
|
|13 |LUT4 | 7196|
|
|
|14 |LUT5 | 11964|
|
|
|15 |LUT6 | 23575|
|
|
|16 |MMCME2_ADV | 1|
|
|
|17 |MUXF7 | 1738|
|
|
|18 |MUXF8 | 139|
|
|
|19 |RAM32M | 225|
|
|
|20 |RAM32X1D | 5|
|
|
|21 |RAMB18E1 | 4|
|
|
|23 |RAMB36E1 | 415|
|
|
|45 |SRL16E | 1|
|
|
|46 |STARTUPE2 | 1|
|
|
|47 |FDCE | 25212|
|
|
|48 |FDPE | 349|
|
|
|49 |FDRE | 9937|
|
|
|50 |FDSE | 119|
|
|
|51 |LDC | 9|
|
|
|52 |IBUF | 7|
|
|
|53 |IBUFDS | 1|
|
|
|54 |IOBUF | 4|
|
|
|55 |OBUF | 10|
|
|
+------+-----------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:03:37 ; elapsed = 00:02:29 . Memory (MB): peak = 3411.289 ; gain = 1541.785 ; free physical = 2982 ; free virtual = 12329
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 587 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:03:26 ; elapsed = 00:02:21 . Memory (MB): peak = 3415.203 ; gain = 1274.605 ; free physical = 9882 ; free virtual = 19232
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:03:37 ; elapsed = 00:02:29 . Memory (MB): peak = 3415.203 ; gain = 1545.699 ; free physical = 9892 ; free virtual = 19233
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.73 . Memory (MB): peak = 3415.203 ; gain = 0.000 ; free physical = 9855 ; free virtual = 19227
|
|
INFO: [Netlist 29-17] Analyzing 8138 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
|
|
Finished Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_rocket.xdc]
|
|
Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
|
|
Finished Parsing XDC File [/home/onur/Desktop/tmp/rocket-chip/hardware/fpga/genesys2/constraints/genesys2_pmod_rf.xdc]
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3580.703 ; gain = 0.000 ; free physical = 9713 ; free virtual = 19129
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 243 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 4 instances
|
|
LDC => LDCE: 9 instances
|
|
RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 225 instances
|
|
RAM32X1D => RAM32X1D (RAMD32(x2)): 5 instances
|
|
|
|
Synth Design complete | Checksum: bcaf9b82
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
648 Infos, 393 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:03:54 ; elapsed = 00:02:47 . Memory (MB): peak = 3580.738 ; gain = 1910.836 ; free physical = 9708 ; free virtual = 19129
|
|
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 10048.543; main = 2793.434; forked = 8221.292
|
|
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 19241.867; main = 3580.707; forked = 16211.785
|
|
# apply_genesys2_async_clock_groups
|
|
Applying Genesys2 async clock groups.
|
|
# write_checkpoint -force [file join $checkpoint_dir post_synth.dcp]
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19127
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19127
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19127
|
|
Wrote PlaceStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19127
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19127
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19127
|
|
Write Physdb Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9663 ; free virtual = 19128
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9652 ; free virtual = 19127
|
|
INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_synth.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 3612.719 ; gain = 31.980 ; free physical = 9510 ; free virtual = 19074
|
|
# report_utilization -hierarchical -file [file join $report_dir synth_utilization_hier.rpt]
|
|
# report_utilization -file [file join $report_dir synth_utilization.rpt]
|
|
# report_timing_summary -file [file join $report_dir synth_timing_summary.rpt]
|
|
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
|
|
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
|
|
report_timing_summary: Time (s): cpu = 00:00:35 ; elapsed = 00:00:08 . Memory (MB): peak = 3612.719 ; gain = 0.000 ; free physical = 9459 ; free virtual = 19064
|
|
# puts "Running implementation..."
|
|
Running implementation...
|
|
# opt_design
|
|
Command: opt_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
|
Running DRC as a precondition to command opt_design
|
|
|
|
Starting DRC Task
|
|
INFO: [DRC 23-27] Running DRC with 12 threads
|
|
INFO: [Project 1-461] DRC finished with 0 Errors
|
|
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
|
|
|
Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.54 . Memory (MB): peak = 3672.047 ; gain = 59.328 ; free physical = 9455 ; free virtual = 19062
|
|
|
|
Starting Cache Timing Information Task
|
|
Ending Cache Timing Information Task | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3672.047 ; gain = 0.000 ; free physical = 9455 ; free virtual = 19062
|
|
|
|
Starting Logic Optimization Task
|
|
|
|
Phase 1 Initialization
|
|
|
|
Phase 1.1 Core Generation And Design Setup
|
|
Phase 1.1 Core Generation And Design Setup | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3696.859 ; gain = 0.000 ; free physical = 9391 ; free virtual = 19007
|
|
|
|
Phase 1.2 Setup Constraints And Sort Netlist
|
|
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.1 . Memory (MB): peak = 3696.859 ; gain = 0.000 ; free physical = 9391 ; free virtual = 19007
|
|
Phase 1 Initialization | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3696.859 ; gain = 0.000 ; free physical = 9391 ; free virtual = 19007
|
|
|
|
Phase 2 Timer Update And Timing Data Collection
|
|
|
|
Phase 2.1 Detect if minReqCache needed
|
|
Phase 2.1 Detect if minReqCache needed | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9366 ; free virtual = 18982
|
|
|
|
Phase 2.2 Timer Update
|
|
Phase 2.2 Timer Update | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:04 ; elapsed = 00:00:01 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9362 ; free virtual = 18984
|
|
|
|
Phase 2.3 Timing Data Collection
|
|
Phase 2.3 Timing Data Collection | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9362 ; free virtual = 18984
|
|
Phase 2 Timer Update And Timing Data Collection | Checksum: 25b6affcd
|
|
|
|
Time (s): cpu = 00:00:05 ; elapsed = 00:00:01 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9362 ; free virtual = 18984
|
|
|
|
Phase 3 Retarget
|
|
INFO: [Opt 31-1851] Number of loadless carry chains removed were: 0
|
|
INFO: [Opt 31-1834] Total Chains To Be Transformed Were: 0 AND Number of Transformed insts Created are: 0
|
|
INFO: [Opt 31-1566] Pulled 36 inverters resulting in an inversion of 1129 pins
|
|
INFO: [Opt 31-138] Pushed 14 inverter(s) to 129 load pin(s).
|
|
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
|
Phase 3 Retarget | Checksum: 1a12a4b58
|
|
|
|
Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9359 ; free virtual = 18987
|
|
Retarget | Checksum: 1a12a4b58
|
|
INFO: [Opt 31-389] Phase Retarget created 474 cells and removed 523 cells
|
|
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 4 Constant propagation
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Phase 4 Constant propagation | Checksum: 267c75149
|
|
|
|
Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9357 ; free virtual = 18990
|
|
Constant propagation | Checksum: 267c75149
|
|
INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells
|
|
|
|
Phase 5 Sweep
|
|
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
|
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3712.859 ; gain = 0.000 ; free physical = 9354 ; free virtual = 18993
|
|
Phase 5 Sweep | Checksum: 21568a1ae
|
|
|
|
Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9350 ; free virtual = 18994
|
|
Sweep | Checksum: 21568a1ae
|
|
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 3 cells
|
|
INFO: [Opt 31-1021] In phase Sweep, 360 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
|
|
|
|
Phase 6 BUFG optimization
|
|
Phase 6 BUFG optimization | Checksum: 21568a1ae
|
|
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9348 ; free virtual = 18993
|
|
BUFG optimization | Checksum: 21568a1ae
|
|
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
|
|
|
Phase 7 Shift Register Optimization
|
|
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
|
Phase 7 Shift Register Optimization | Checksum: 21568a1ae
|
|
|
|
Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9348 ; free virtual = 18993
|
|
Shift Register Optimization | Checksum: 21568a1ae
|
|
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
|
|
|
Phase 8 Post Processing Netlist
|
|
Phase 8 Post Processing Netlist | Checksum: 21568a1ae
|
|
|
|
Time (s): cpu = 00:00:09 ; elapsed = 00:00:05 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9347 ; free virtual = 18992
|
|
Post Processing Netlist | Checksum: 21568a1ae
|
|
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
|
|
|
Phase 9 Finalization
|
|
|
|
Phase 9.1 Finalizing Design Cores and Updating Shapes
|
|
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 12670944f
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9352 ; free virtual = 19009
|
|
|
|
Phase 9.2 Verifying Netlist Connectivity
|
|
|
|
Starting Connectivity Check Task
|
|
|
|
Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3712.859 ; gain = 0.000 ; free physical = 9351 ; free virtual = 19010
|
|
Phase 9.2 Verifying Netlist Connectivity | Checksum: 12670944f
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9351 ; free virtual = 19010
|
|
Phase 9 Finalization | Checksum: 12670944f
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9351 ; free virtual = 19010
|
|
Opt_design Change Summary
|
|
=========================
|
|
|
|
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
| Retarget | 474 | 523 | 1 |
|
|
| Constant propagation | 1 | 1 | 0 |
|
|
| Sweep | 0 | 3 | 360 |
|
|
| BUFG optimization | 0 | 0 | 0 |
|
|
| Shift Register Optimization | 0 | 0 | 0 |
|
|
| Post Processing Netlist | 0 | 0 | 0 |
|
|
-------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Ending Logic Optimization Task | Checksum: 12670944f
|
|
|
|
Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 3712.859 ; gain = 16.000 ; free physical = 9351 ; free virtual = 19009
|
|
|
|
Starting Power Optimization Task
|
|
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
|
INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Running Vector-less Activity Propagation...
|
|
|
|
Finished Running Vector-less Activity Propagation
|
|
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
|
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
|
|
|
|
|
Starting PowerOpt Patch Enables Task
|
|
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 419 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
|
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
|
Number of BRAM Ports augmented: 0 newly gated: 84 Total Ports: 838
|
|
Ending PowerOpt Patch Enables Task | Checksum: 1b1113d5b
|
|
|
|
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8753 ; free virtual = 18550
|
|
Ending Power Optimization Task | Checksum: 1b1113d5b
|
|
|
|
Time (s): cpu = 00:00:38 ; elapsed = 00:00:22 . Memory (MB): peak = 4301.789 ; gain = 588.930 ; free physical = 8753 ; free virtual = 18551
|
|
|
|
Starting Final Cleanup Task
|
|
|
|
Starting Logic Optimization Task
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Ending Logic Optimization Task | Checksum: 187bdb3d5
|
|
|
|
Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18522
|
|
Ending Final Cleanup Task | Checksum: 187bdb3d5
|
|
|
|
Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18523
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18523
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
opt_design completed successfully
|
|
opt_design: Time (s): cpu = 00:01:05 ; elapsed = 00:00:36 . Memory (MB): peak = 4301.789 ; gain = 689.070 ; free physical = 8702 ; free virtual = 18523
|
|
# write_checkpoint -force [file join $checkpoint_dir post_opt.dcp]
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18524
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18524
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18524
|
|
Wrote PlaceStorage: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18524
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18524
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18525
|
|
Write Physdb Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8702 ; free virtual = 18525
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.12 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8693 ; free virtual = 18527
|
|
INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_opt.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8575 ; free virtual = 18463
|
|
# place_design
|
|
Command: place_design
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
INFO: [DRC 23-27] Running DRC with 12 threads
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
Running DRC as a precondition to command place_design
|
|
INFO: [DRC 23-27] Running DRC with 12 threads
|
|
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 42 Warnings
|
|
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
|
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 12 CPUs
|
|
|
|
Starting Placer Task
|
|
|
|
Phase 1 Placer Initialization
|
|
|
|
Phase 1.1 Placer Initialization Netlist Sorting
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8576 ; free virtual = 18483
|
|
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15542224b
|
|
|
|
Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8576 ; free virtual = 18483
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8575 ; free virtual = 18482
|
|
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
|
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 55a25485
|
|
|
|
Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8581 ; free virtual = 18501
|
|
|
|
Phase 1.3 Build Placer Netlist Model
|
|
Phase 1.3 Build Placer Netlist Model | Checksum: aed9a21a
|
|
|
|
Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8443 ; free virtual = 18493
|
|
|
|
Phase 1.4 Constrain Clocks/Macros
|
|
Phase 1.4 Constrain Clocks/Macros | Checksum: aed9a21a
|
|
|
|
Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8441 ; free virtual = 18492
|
|
Phase 1 Placer Initialization | Checksum: aed9a21a
|
|
|
|
Time (s): cpu = 00:00:51 ; elapsed = 00:00:18 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8441 ; free virtual = 18493
|
|
|
|
Phase 2 Global Placement
|
|
|
|
Phase 2.1 Floorplanning
|
|
Phase 2.1 Floorplanning | Checksum: 1097d1fc4
|
|
|
|
Time (s): cpu = 00:01:19 ; elapsed = 00:00:24 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8450 ; free virtual = 18549
|
|
|
|
Phase 2.2 Update Timing before SLR Path Opt
|
|
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 140cb971d
|
|
|
|
Time (s): cpu = 00:01:46 ; elapsed = 00:00:30 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8410 ; free virtual = 18538
|
|
|
|
Phase 2.3 Post-Processing in Floorplanning
|
|
Phase 2.3 Post-Processing in Floorplanning | Checksum: 140cb971d
|
|
|
|
Time (s): cpu = 00:01:47 ; elapsed = 00:00:30 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8410 ; free virtual = 18538
|
|
|
|
Phase 2.4 Global Place Phase1
|
|
Phase 2.4 Global Place Phase1 | Checksum: 1529dbc1b
|
|
|
|
Time (s): cpu = 00:03:17 ; elapsed = 00:01:01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8483 ; free virtual = 18611
|
|
|
|
Phase 2.5 Global Place Phase2
|
|
|
|
Phase 2.5.1 UpdateTiming Before Physical Synthesis
|
|
Phase 2.5.1 UpdateTiming Before Physical Synthesis | Checksum: b1463a6a
|
|
|
|
Time (s): cpu = 00:03:46 ; elapsed = 00:01:07 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8481 ; free virtual = 18609
|
|
|
|
Phase 2.5.2 Physical Synthesis In Placer
|
|
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 3898 LUT instances to create LUTNM shape
|
|
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
|
INFO: [Physopt 32-1138] End 1 Pass. Optimized 987 nets or LUTs. Breaked 0 LUT, combined 987 existing LUTs and moved 0 existing LUT
|
|
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
|
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
|
|
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
|
|
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization.
|
|
INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
|
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8476 ; free virtual = 18607
|
|
|
|
Summary of Physical Synthesis Optimizations
|
|
============================================
|
|
|
|
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
| LUT Combining | 0 | 987 | 987 | 0 | 1 | 00:00:02 |
|
|
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
|
| Total | 0 | 987 | 987 | 0 | 9 | 00:00:02 |
|
|
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Phase 2.5.2 Physical Synthesis In Placer | Checksum: 1880d0d56
|
|
|
|
Time (s): cpu = 00:04:16 ; elapsed = 00:01:16 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8476 ; free virtual = 18607
|
|
Phase 2.5 Global Place Phase2 | Checksum: 26c844ba1
|
|
|
|
Time (s): cpu = 00:04:21 ; elapsed = 00:01:19 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8475 ; free virtual = 18606
|
|
Phase 2 Global Placement | Checksum: 26c844ba1
|
|
|
|
Time (s): cpu = 00:04:21 ; elapsed = 00:01:19 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8475 ; free virtual = 18606
|
|
|
|
Phase 3 Detail Placement
|
|
|
|
Phase 3.1 Commit Multi Column Macros
|
|
Phase 3.1 Commit Multi Column Macros | Checksum: 2f5e60293
|
|
|
|
Time (s): cpu = 00:04:48 ; elapsed = 00:01:25 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8475 ; free virtual = 18606
|
|
|
|
Phase 3.2 Commit Most Macros & LUTRAMs
|
|
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 15486e37f
|
|
|
|
Time (s): cpu = 00:05:38 ; elapsed = 00:01:37 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8474 ; free virtual = 18606
|
|
|
|
Phase 3.3 Area Swap Optimization
|
|
Phase 3.3 Area Swap Optimization | Checksum: 1caafb47f
|
|
|
|
Time (s): cpu = 00:05:39 ; elapsed = 00:01:37 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8474 ; free virtual = 18606
|
|
|
|
Phase 3.4 Pipeline Register Optimization
|
|
Phase 3.4 Pipeline Register Optimization | Checksum: 236ca933b
|
|
|
|
Time (s): cpu = 00:05:39 ; elapsed = 00:01:37 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8474 ; free virtual = 18606
|
|
|
|
Phase 3.5 Fast Optimization
|
|
Phase 3.5 Fast Optimization | Checksum: 182d47727
|
|
|
|
Time (s): cpu = 00:06:32 ; elapsed = 00:01:48 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8481 ; free virtual = 18612
|
|
|
|
Phase 3.6 Small Shape Detail Placement
|
|
Phase 3.6 Small Shape Detail Placement | Checksum: 1e2994576
|
|
|
|
Time (s): cpu = 00:06:58 ; elapsed = 00:02:25 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8420 ; free virtual = 18557
|
|
|
|
Phase 3.7 Re-assign LUT pins
|
|
Phase 3.7 Re-assign LUT pins | Checksum: 22381ffca
|
|
|
|
Time (s): cpu = 00:07:03 ; elapsed = 00:02:29 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8429 ; free virtual = 18566
|
|
|
|
Phase 3.8 Pipeline Register Optimization
|
|
Phase 3.8 Pipeline Register Optimization | Checksum: 16d34e0b6
|
|
|
|
Time (s): cpu = 00:07:03 ; elapsed = 00:02:29 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8429 ; free virtual = 18565
|
|
|
|
Phase 3.9 Fast Optimization
|
|
Phase 3.9 Fast Optimization | Checksum: 268a117e1
|
|
|
|
Time (s): cpu = 00:08:11 ; elapsed = 00:02:43 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8455 ; free virtual = 18591
|
|
Phase 3 Detail Placement | Checksum: 268a117e1
|
|
|
|
Time (s): cpu = 00:08:12 ; elapsed = 00:02:43 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8454 ; free virtual = 18591
|
|
|
|
Phase 4 Post Placement Optimization and Clean-Up
|
|
|
|
Phase 4.1 Post Commit Optimization
|
|
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
|
|
|
Phase 4.1.1 Post Placement Optimization
|
|
Post Placement Optimization Initialization | Checksum: 16302e930
|
|
|
|
Phase 4.1.1.1 BUFG Insertion
|
|
|
|
Starting Physical Synthesis Task
|
|
|
|
Phase 1 Physical Synthesis Initialization
|
|
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 12 CPUs
|
|
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-0.702 | TNS=-5.552 |
|
|
Phase 1 Physical Synthesis Initialization | Checksum: 92d1356a
|
|
|
|
Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.63 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8434 ; free virtual = 18571
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/sync_0_reg, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_0/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_1, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_1/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_2/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_3/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_4/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_5/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_6/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_7/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-33] Processed net u_rocket/fpga_gps_domain/dev/tracking_8/i_trck_top/trck_cntrl_i/stop_in_trk_r2_reg_0, BUFG insertion was skipped due to placement/routing conflicts.
|
|
INFO: [Place 46-56] BUFG insertion identified 10 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 10, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
|
Ending Physical Synthesis Task | Checksum: 16d627385
|
|
|
|
Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8436 ; free virtual = 18573
|
|
Phase 4.1.1.1 BUFG Insertion | Checksum: 16302e930
|
|
|
|
Time (s): cpu = 00:09:02 ; elapsed = 00:02:55 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8436 ; free virtual = 18573
|
|
|
|
Phase 4.1.1.2 Post Placement Timing Optimization
|
|
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.100. For the most accurate timing information please run report_timing.
|
|
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1063d84bd
|
|
|
|
Time (s): cpu = 00:10:13 ; elapsed = 00:03:20 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
|
|
Time (s): cpu = 00:10:13 ; elapsed = 00:03:20 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
Phase 4.1 Post Commit Optimization | Checksum: 1063d84bd
|
|
|
|
Time (s): cpu = 00:10:13 ; elapsed = 00:03:20 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
|
|
Phase 4.2 Post Placement Cleanup
|
|
Phase 4.2 Post Placement Cleanup | Checksum: 1063d84bd
|
|
|
|
Time (s): cpu = 00:10:14 ; elapsed = 00:03:21 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
|
|
Phase 4.3 Placer Reporting
|
|
|
|
Phase 4.3.1 Print Estimated Congestion
|
|
INFO: [Place 30-612] Post-Placement Estimated Congestion
|
|
____________________________________________________
|
|
| | Global Congestion | Short Congestion |
|
|
| Direction | Region Size | Region Size |
|
|
|___________|___________________|___________________|
|
|
| North| 1x1| 4x4|
|
|
|___________|___________________|___________________|
|
|
| South| 1x1| 4x4|
|
|
|___________|___________________|___________________|
|
|
| East| 2x2| 4x4|
|
|
|___________|___________________|___________________|
|
|
| West| 1x1| 2x2|
|
|
|___________|___________________|___________________|
|
|
|
|
Phase 4.3.1 Print Estimated Congestion | Checksum: 1063d84bd
|
|
|
|
Time (s): cpu = 00:10:14 ; elapsed = 00:03:21 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
Phase 4.3 Placer Reporting | Checksum: 1063d84bd
|
|
|
|
Time (s): cpu = 00:10:15 ; elapsed = 00:03:21 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
|
|
Phase 4.4 Final Placement Cleanup
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
|
|
Time (s): cpu = 00:10:15 ; elapsed = 00:03:21 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1732515a3
|
|
|
|
Time (s): cpu = 00:10:15 ; elapsed = 00:03:21 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
Ending Placer Task | Checksum: 158e08fcc
|
|
|
|
Time (s): cpu = 00:10:16 ; elapsed = 00:03:21 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
47 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
place_design completed successfully
|
|
place_design: Time (s): cpu = 00:10:26 ; elapsed = 00:03:25 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
# write_checkpoint -force [file join $checkpoint_dir post_place.dcp]
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18575
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8438 ; free virtual = 18576
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.14 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8415 ; free virtual = 18570
|
|
Wrote PlaceStorage: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8309 ; free virtual = 18549
|
|
Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8290 ; free virtual = 18538
|
|
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8290 ; free virtual = 18538
|
|
Write Physdb Complete: Time (s): cpu = 00:00:06 ; elapsed = 00:00:02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8290 ; free virtual = 18538
|
|
INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_place.dcp' has been generated.
|
|
write_checkpoint: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8337 ; free virtual = 18536
|
|
# phys_opt_design -directive Explore
|
|
Command: phys_opt_design -directive Explore
|
|
Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
|
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
|
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
|
|
|
|
Starting Initial Update Timing Task
|
|
|
|
Time (s): cpu = 00:00:41 ; elapsed = 00:00:08 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8349 ; free virtual = 18548
|
|
INFO: [Vivado_Tcl 4-2279] Estimated Timing Summary | WNS= 0.106 | TNS= 0.000 |
|
|
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. All physical synthesis setup optimizations will be skipped.
|
|
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
|
|
INFO: [Common 17-83] Releasing license: Implementation
|
|
6 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
phys_opt_design completed successfully
|
|
phys_opt_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:09 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8349 ; free virtual = 18548
|
|
# write_checkpoint -force [file join $checkpoint_dir post_phys_opt.dcp]
|
|
INFO: [Timing 38-480] Writing timing data to binary archive.
|
|
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8349 ; free virtual = 18548
|
|
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8349 ; free virtual = 18548
|
|
Writing XDEF routing.
|
|
Writing XDEF routing logical nets.
|
|
Writing XDEF routing special nets.
|
|
Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8349 ; free virtual = 18549
|
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.15 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8333 ; free virtual = 18551
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Wrote PlaceStorage: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8233 ; free virtual = 18535
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Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8225 ; free virtual = 18535
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Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8225 ; free virtual = 18536
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Write Physdb Complete: Time (s): cpu = 00:00:07 ; elapsed = 00:00:02 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8225 ; free virtual = 18536
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INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_phys_opt.dcp' has been generated.
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write_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8262 ; free virtual = 18523
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# route_design
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Command: route_design
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
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Starting Routing Task
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INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 12 CPUs
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Phase 1 Build RT Design
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Checksum: PlaceDB: 8b43e7eb ConstDB: 0 ShapeSum: a5212d91 RouteDB: 287b7a50
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Post Restoration Checksum: NetGraph: f7ca027e | NumContArr: 48ab044e | Constraints: c2a8fa9d | Timing: c2a8fa9d
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Phase 1 Build RT Design | Checksum: 2c5c6fc06
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Time (s): cpu = 00:00:58 ; elapsed = 00:00:20 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8352 ; free virtual = 18616
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Phase 2 Router Initialization
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Phase 2.1 Fix Topology Constraints
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Phase 2.1 Fix Topology Constraints | Checksum: 2c5c6fc06
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Time (s): cpu = 00:00:59 ; elapsed = 00:00:20 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8352 ; free virtual = 18616
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Phase 2.2 Pre Route Cleanup
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Phase 2.2 Pre Route Cleanup | Checksum: 2c5c6fc06
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Time (s): cpu = 00:00:59 ; elapsed = 00:00:20 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8352 ; free virtual = 18616
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Number of Nodes with overlaps = 0
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Phase 2.3 Update Timing
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Phase 2.3 Update Timing | Checksum: 217260bff
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Time (s): cpu = 00:01:56 ; elapsed = 00:00:32 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8353 ; free virtual = 18618
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.036 | TNS=0.000 | WHS=-0.368 | THS=-1857.985|
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Phase 2.4 Soft Constraint Pins - Fast Budgeting
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Phase 2.4 Soft Constraint Pins - Fast Budgeting | Checksum: 1bea14b3c
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Time (s): cpu = 00:02:09 ; elapsed = 00:00:35 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8353 ; free virtual = 18617
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Router Utilization Summary
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Global Vertical Routing Utilization = 0.00164574 %
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Global Horizontal Routing Utilization = 0.00141269 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 92497
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(Failed Nets is the sum of unrouted and partially routed nets)
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Number of Unrouted Nets = 92479
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Number of Partially Routed Nets = 18
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Number of Node Overlaps = 2
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Phase 2 Router Initialization | Checksum: 244981815
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Time (s): cpu = 00:02:11 ; elapsed = 00:00:35 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8321 ; free virtual = 18586
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Phase 3 Global Routing
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Phase 3 Global Routing | Checksum: 244981815
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Time (s): cpu = 00:02:11 ; elapsed = 00:00:35 . Memory (MB): peak = 4301.789 ; gain = 0.000 ; free physical = 8321 ; free virtual = 18586
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Phase 4 Initial Routing
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Phase 4.1 Initial Net Routing Pass
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Phase 4.1 Initial Net Routing Pass | Checksum: 2eb0eb30b
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Time (s): cpu = 00:03:25 ; elapsed = 00:00:54 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7816 ; free virtual = 18080
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Phase 4 Initial Routing | Checksum: 2eb0eb30b
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Time (s): cpu = 00:03:25 ; elapsed = 00:00:54 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7817 ; free virtual = 18082
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Phase 5 Rip-up And Reroute
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Phase 5.1 Global Iteration 0
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Number of Nodes with overlaps = 8355
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Number of Nodes with overlaps = 47
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Number of Nodes with overlaps = 4
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Number of Nodes with overlaps = 1
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Number of Nodes with overlaps = 0
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.257 | TNS=0.000 | WHS=N/A | THS=N/A |
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Phase 5.1 Global Iteration 0 | Checksum: 2a819cb5c
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Time (s): cpu = 00:04:27 ; elapsed = 00:01:18 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 5 Rip-up And Reroute | Checksum: 2a819cb5c
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Time (s): cpu = 00:04:27 ; elapsed = 00:01:18 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 6 Delay and Skew Optimization
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Phase 6.1 Delay CleanUp
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Phase 6.1 Delay CleanUp | Checksum: 2a819cb5c
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Time (s): cpu = 00:04:27 ; elapsed = 00:01:18 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 6.2 Clock Skew Optimization
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Phase 6.2 Clock Skew Optimization | Checksum: 2a819cb5c
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Time (s): cpu = 00:04:28 ; elapsed = 00:01:18 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 6 Delay and Skew Optimization | Checksum: 2a819cb5c
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Time (s): cpu = 00:04:28 ; elapsed = 00:01:18 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 7 Post Hold Fix
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Phase 7.1 Hold Fix Iter
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INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.275 | TNS=0.000 | WHS=0.063 | THS=0.000 |
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Phase 7.1 Hold Fix Iter | Checksum: 1fc79f4b9
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Time (s): cpu = 00:04:35 ; elapsed = 00:01:19 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 7 Post Hold Fix | Checksum: 1fc79f4b9
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Time (s): cpu = 00:04:35 ; elapsed = 00:01:19 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 8 Route finalize
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Router Utilization Summary
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Global Vertical Routing Utilization = 8.43263 %
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Global Horizontal Routing Utilization = 8.87763 %
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Routable Net Status*
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*Does not include unroutable nets such as driverless and loadless.
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Run report_route_status for detailed report.
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Number of Failed Nets = 0
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(Failed Nets is the sum of unrouted and partially routed nets)
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Number of Unrouted Nets = 0
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Number of Partially Routed Nets = 0
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Number of Node Overlaps = 0
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Phase 8 Route finalize | Checksum: 1fc79f4b9
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Time (s): cpu = 00:04:36 ; elapsed = 00:01:19 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 9 Verifying routed nets
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Verification completed successfully
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Phase 9 Verifying routed nets | Checksum: 1fc79f4b9
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Time (s): cpu = 00:04:36 ; elapsed = 00:01:19 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 10 Depositing Routes
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Phase 10 Depositing Routes | Checksum: 24ab965a1
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Time (s): cpu = 00:04:46 ; elapsed = 00:01:25 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 11 Post Process Routing
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Phase 11 Post Process Routing | Checksum: 24ab965a1
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Time (s): cpu = 00:04:46 ; elapsed = 00:01:25 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Phase 12 Post Router Timing
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INFO: [Route 35-57] Estimated Timing Summary | WNS=0.275 | TNS=0.000 | WHS=0.063 | THS=0.000 |
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INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
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Phase 12 Post Router Timing | Checksum: 24ab965a1
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Time (s): cpu = 00:04:46 ; elapsed = 00:01:25 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Total Elapsed time in route_design: 84.81 secs
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Phase 13 Post-Route Event Processing
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Phase 13 Post-Route Event Processing | Checksum: 1589614c7
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Time (s): cpu = 00:04:47 ; elapsed = 00:01:25 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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INFO: [Route 35-16] Router Completed Successfully
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Ending Routing Task | Checksum: 1589614c7
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Time (s): cpu = 00:04:48 ; elapsed = 00:01:25 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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Routing Is Done.
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INFO: [Common 17-83] Releasing license: Implementation
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9 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
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route_design completed successfully
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route_design: Time (s): cpu = 00:04:48 ; elapsed = 00:01:25 . Memory (MB): peak = 4662.738 ; gain = 360.949 ; free physical = 7831 ; free virtual = 18096
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# write_checkpoint -force [file join $checkpoint_dir post_route.dcp]
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INFO: [Timing 38-480] Writing timing data to binary archive.
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Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7831 ; free virtual = 18096
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Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7831 ; free virtual = 18096
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Writing XDEF routing.
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Writing XDEF routing logical nets.
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Write ShapeDB Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.17 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7819 ; free virtual = 18100
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Writing XDEF routing special nets.
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Wrote RouteStorage: Time (s): cpu = 00:00:07 ; elapsed = 00:00:01 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7785 ; free virtual = 18108
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Wrote PlaceStorage: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7717 ; free virtual = 18103
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Wrote Netlist Cache: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.08 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7701 ; free virtual = 18096
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Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7701 ; free virtual = 18097
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Write Physdb Complete: Time (s): cpu = 00:00:11 ; elapsed = 00:00:03 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7701 ; free virtual = 18097
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INFO: [Common 17-1381] The checkpoint '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/build/checkpoints/post_route.dcp' has been generated.
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write_checkpoint: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7749 ; free virtual = 18084
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# report_utilization -file [file join $report_dir route_utilization.rpt]
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# report_timing_summary -file [file join $report_dir route_timing_summary.rpt]
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INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
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INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 12 CPUs
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report_timing_summary: Time (s): cpu = 00:00:42 ; elapsed = 00:00:07 . Memory (MB): peak = 4662.738 ; gain = 0.000 ; free physical = 7732 ; free virtual = 18067
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# report_drc -file [file join $report_dir route_drc.rpt]
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Command: report_drc -file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/2025.2/data/ip'.
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INFO: [DRC 23-27] Running DRC with 12 threads
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INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/reports/route_drc.rpt.
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report_drc completed successfully
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# report_power -file [file join $report_dir route_power.rpt]
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Command: report_power -file /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/reports/route_power.rpt
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INFO: [Power 33-23] Power model is not available for u_cfg_flash_startup
|
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Running Vector-less Activity Propagation...
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Finished Running Vector-less Activity Propagation
|
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WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
|
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Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
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1 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
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report_power completed successfully
|
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report_power: Time (s): cpu = 00:00:22 ; elapsed = 00:00:10 . Memory (MB): peak = 4766.789 ; gain = 104.051 ; free physical = 7727 ; free virtual = 18070
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# set bit_file [file join $bit_dir genesys2_rocket.bit]
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# puts "Writing bitstream: $bit_file"
|
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Writing bitstream: /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
|
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# write_bitstream -force $bit_file
|
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Command: write_bitstream -force /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit
|
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Attempting to get a license for feature 'Implementation' and/or device 'xc7k325t'
|
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INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t'
|
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Running DRC as a precondition to command write_bitstream
|
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INFO: [IP_Flow 19-1839] IP Catalog is up to date.
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INFO: [DRC 23-27] Running DRC with 12 threads
|
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INFO: [Vivado 12-3199] DRC finished with 0 Errors
|
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INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
|
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Integrating Hard IP ELF/MEM with the PDI.
|
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INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
|
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Loading data files...
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Loading site data...
|
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Loading route data...
|
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Processing options...
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Creating bitmap...
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Creating bitstream...
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Writing bitstream /home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2/out/bitstream/genesys2_rocket.bit...
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INFO: [Vivado 12-1842] Bitgen Completed Successfully.
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INFO: [Common 17-83] Releasing license: Implementation
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8 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
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write_bitstream completed successfully
|
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write_bitstream: Time (s): cpu = 00:02:00 ; elapsed = 00:00:23 . Memory (MB): peak = 4785.824 ; gain = 19.035 ; free physical = 7650 ; free virtual = 18007
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# puts "Genesys2 non-project flow complete."
|
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Genesys2 non-project flow complete.
|
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INFO: [Common 17-206] Exiting Vivado at Tue Jul 7 17:42:59 2026...
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make[1]: Leaving directory '/home/onur/Desktop/tmp/rocket-chip/targets/fpga/genesys2'
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