50 lines
2.1 KiB
TableGen
50 lines
2.1 KiB
TableGen
//===-- AMDGPUAttrs.td - AMDGPU dialect attributes *- tablegen -*----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_DIALECT_AMDGPU_IR_AMDGPUATTRS_TD
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#define MLIR_DIALECT_AMDGPU_IR_AMDGPUATTRS_TD
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include "mlir/Dialect/AMDGPU/IR/AMDGPUBase.td"
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include "mlir/Dialect/AMDGPU/IR/AMDGPUEnums.td"
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include "mlir/Dialect/LLVMIR/ROCDLAttrs.td"
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def AMDGPU_AddressSpaceAttr : EnumAttr<AMDGPU_Dialect, AMDGPU_AddressSpace,
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"address_space"> {
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let description = [{
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AMDGPU-specific memory spaces that may not have exact analogues on other
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GPU targets or backends.
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- `fat_raw_buffer` is the memory space used when a memref is stored as
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as a "buffer fat pointer" - that is, a buffer resource (that is set up to
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use raw byte-level indexing) along with its offset. The AMDGPU backend
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implements `ptr addrspace(7)` to represent these fat pointers so that
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buffer resources (which allow advanced features like bounds checking or
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cache swizzling) can be used like ordinary LLVM pointers or memrefs.
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See also the `fat_raw_buffer_cast` operation
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- `buffer_rsrc` is the memory space for `ptr addrspace(8)`, representing a
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buffer resource. It should not be used for memrefs, since it does not support
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indexing
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- `fat_structured_buffer` represents `ptr addrspace(9)`, a buffer resource
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that carries both an index and offset field, which are used for complex
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structured indexing that is primarily seen in graphics applications. This
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is also incompatible with the simple indexing model supported by memref.
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}];
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let assemblyFormat = "`<` $value `>`";
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}
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def AMDGPU_DPPPermAttr : EnumAttr<AMDGPU_Dialect, AMDGPU_DPPPerm,
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"dpp_perm">;
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def AMDGPU_LoadTemporalHintAttr : EnumAttr<AMDGPU_Dialect, AMDGPU_LoadTemporalHint,
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"load_temporal_hint">;
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def AMDGPU_CacheScopeAttr : EnumAttr<AMDGPU_Dialect, AMDGPU_CacheScope,
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"cache_scope">;
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#endif // MLIR_DIALECT_AMDGPU_IR_AMDGPUATTRS_TD
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