38 lines
1.5 KiB
C++
38 lines
1.5 KiB
C++
//===- Utils.h - General AMDGPU Enums utilities -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef MLIR_DIALECT_AMDGPU_UTILS_AMDGPU_ENUMS_H_
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#define MLIR_DIALECT_AMDGPU_UTILS_AMDGPU_ENUMS_H_
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#include "mlir/Dialect/AMDGPU/IR/AMDGPUEnums.h.inc"
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#include "mlir/IR/BuiltinAttributeInterfaces.h"
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#include "mlir/IR/OpImplementation.h"
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#include "llvm/ADT/STLExtras.h"
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namespace mlir::amdgpu {
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inline int32_t getGlobalPrefetchLLVMEncoding(amdgpu::LoadTemporalHint hint,
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amdgpu::Scope scope,
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bool isSpeculative) {
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int32_t immArg = static_cast<int32_t>(hint);
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// Note that only RT and HT can operate in both speculative and
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// non-speculative modes. The other variants (NT_RT, RT_NT, NT_HT, etc.)
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// operate only in the speculative mode and, therefore, do not require
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// toggling the least significant bit for mode changes
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// Temporal hint is encoded in lower bits - i.e. [2:0]
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if (llvm::is_contained({LoadTemporalHint::RT, LoadTemporalHint::HT}, hint))
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immArg = isSpeculative ? immArg : immArg | 1;
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// Prefetch scope level is encoded in upper bits - i.e., [4:3]
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return static_cast<int32_t>(scope) << 3 | immArg;
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}
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} // namespace mlir::amdgpu
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#endif
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