Files
gps/targets/fpga/vcu118/flow/debug
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..
2026-07-12 11:01:51 +03:00
2026-07-12 11:01:51 +03:00
2026-07-12 11:01:51 +03:00
2026-07-12 11:01:51 +03:00
2026-07-12 11:01:51 +03:00

VCU118 GDB Debug Flow

Use this after the VCU118 bitstream is already programmed.

Terminal 1:

make -C targets/fpga/vcu118 debug-openocd

Terminal 2:

make -C targets/fpga/vcu118 uart-listen UART_PORT=/dev/ttyUSB2

Terminal 3:

make -C targets/fpga/vcu118 debug-load APP=hello_uart

Expected UART output starts with:

Rocket Chip VCU118 hello printf

Notes:

  • OpenOCD uses Xilinx BSCAN, not a direct external RISC-V TAP.
  • rocket_bscan_dmi_tunnel.sv must be present in the FPGA bitstream.
  • If OpenOCD reports LIBUSB_ERROR_BUSY, close Vivado Hardware Manager or kill stale hw_server processes.