168 lines
5.7 KiB
C++
168 lines
5.7 KiB
C++
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|* *|
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|* Enum Utility Definitions *|
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|* *|
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|* Automatically generated file, do not edit! *|
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|* From: AMDGPUEnums.td *|
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|* *|
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\*===----------------------------------------------------------------------===*/
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namespace mlir::amdgpu {
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::llvm::StringRef stringifyAddressSpace(AddressSpace val) {
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switch (val) {
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case AddressSpace::FatRawBuffer: return "fat_raw_buffer";
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case AddressSpace::BufferRsrc: return "buffer_rsrc";
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case AddressSpace::FatStructuredBuffer: return "fat_structured_buffer";
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}
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return "";
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}
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::std::optional<AddressSpace> symbolizeAddressSpace(::llvm::StringRef str) {
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return ::llvm::StringSwitch<::std::optional<AddressSpace>>(str)
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.Case("fat_raw_buffer", AddressSpace::FatRawBuffer)
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.Case("buffer_rsrc", AddressSpace::BufferRsrc)
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.Case("fat_structured_buffer", AddressSpace::FatStructuredBuffer)
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.Default(::std::nullopt);
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}
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::std::optional<AddressSpace> symbolizeAddressSpace(uint32_t value) {
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switch (value) {
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case 0: return AddressSpace::FatRawBuffer;
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case 1: return AddressSpace::BufferRsrc;
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case 2: return AddressSpace::FatStructuredBuffer;
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default: return ::std::nullopt;
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}
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}
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} // namespace mlir::amdgpu
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namespace mlir::amdgpu {
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::llvm::StringRef stringifyScope(Scope val) {
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switch (val) {
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case Scope::WGP: return "WGP";
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case Scope::SE: return "SE";
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case Scope::DEV: return "DEV";
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case Scope::SYS: return "SYS";
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}
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return "";
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}
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::std::optional<Scope> symbolizeScope(::llvm::StringRef str) {
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return ::llvm::StringSwitch<::std::optional<Scope>>(str)
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.Case("WGP", Scope::WGP)
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.Case("SE", Scope::SE)
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.Case("DEV", Scope::DEV)
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.Case("SYS", Scope::SYS)
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.Default(::std::nullopt);
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}
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::std::optional<Scope> symbolizeScope(uint32_t value) {
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switch (value) {
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case 0: return Scope::WGP;
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case 1: return Scope::SE;
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case 2: return Scope::DEV;
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case 3: return Scope::SYS;
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default: return ::std::nullopt;
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}
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}
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} // namespace mlir::amdgpu
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namespace mlir::amdgpu {
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::llvm::StringRef stringifyDPPPerm(DPPPerm val) {
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switch (val) {
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case DPPPerm::quad_perm: return "quad_perm";
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case DPPPerm::row_shl: return "row_shl";
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case DPPPerm::row_shr: return "row_shr";
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case DPPPerm::row_ror: return "row_ror";
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case DPPPerm::wave_shl: return "wave_shl";
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case DPPPerm::wave_shr: return "wave_shr";
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case DPPPerm::wave_ror: return "wave_ror";
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case DPPPerm::wave_rol: return "wave_rol";
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case DPPPerm::row_mirror: return "row_mirror";
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case DPPPerm::row_half_mirror: return "row_half_mirror";
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case DPPPerm::row_bcast_15: return "row_bcast_15";
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case DPPPerm::row_bcast_31: return "row_bcast_31";
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}
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return "";
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}
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::std::optional<DPPPerm> symbolizeDPPPerm(::llvm::StringRef str) {
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return ::llvm::StringSwitch<::std::optional<DPPPerm>>(str)
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.Case("quad_perm", DPPPerm::quad_perm)
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.Case("row_shl", DPPPerm::row_shl)
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.Case("row_shr", DPPPerm::row_shr)
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.Case("row_ror", DPPPerm::row_ror)
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.Case("wave_shl", DPPPerm::wave_shl)
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.Case("wave_shr", DPPPerm::wave_shr)
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.Case("wave_ror", DPPPerm::wave_ror)
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.Case("wave_rol", DPPPerm::wave_rol)
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.Case("row_mirror", DPPPerm::row_mirror)
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.Case("row_half_mirror", DPPPerm::row_half_mirror)
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.Case("row_bcast_15", DPPPerm::row_bcast_15)
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.Case("row_bcast_31", DPPPerm::row_bcast_31)
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.Default(::std::nullopt);
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}
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::std::optional<DPPPerm> symbolizeDPPPerm(uint32_t value) {
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switch (value) {
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case 0: return DPPPerm::quad_perm;
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case 1: return DPPPerm::row_shl;
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case 2: return DPPPerm::row_shr;
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case 3: return DPPPerm::row_ror;
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case 4: return DPPPerm::wave_shl;
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case 5: return DPPPerm::wave_shr;
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case 6: return DPPPerm::wave_ror;
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case 7: return DPPPerm::wave_rol;
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case 8: return DPPPerm::row_mirror;
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case 9: return DPPPerm::row_half_mirror;
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case 10: return DPPPerm::row_bcast_15;
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case 11: return DPPPerm::row_bcast_31;
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default: return ::std::nullopt;
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}
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}
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} // namespace mlir::amdgpu
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namespace mlir::amdgpu {
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::llvm::StringRef stringifyLoadTemporalHint(LoadTemporalHint val) {
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switch (val) {
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case LoadTemporalHint::RT: return "RT";
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case LoadTemporalHint::NT: return "NT";
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case LoadTemporalHint::HT: return "HT";
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case LoadTemporalHint::LU: return "LU";
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case LoadTemporalHint::NT_RT: return "NT_RT";
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case LoadTemporalHint::RT_NT: return "RT_NT";
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case LoadTemporalHint::NT_HT: return "NT_HT";
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}
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return "";
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}
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::std::optional<LoadTemporalHint> symbolizeLoadTemporalHint(::llvm::StringRef str) {
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return ::llvm::StringSwitch<::std::optional<LoadTemporalHint>>(str)
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.Case("RT", LoadTemporalHint::RT)
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.Case("NT", LoadTemporalHint::NT)
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.Case("HT", LoadTemporalHint::HT)
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.Case("LU", LoadTemporalHint::LU)
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.Case("NT_RT", LoadTemporalHint::NT_RT)
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.Case("RT_NT", LoadTemporalHint::RT_NT)
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.Case("NT_HT", LoadTemporalHint::NT_HT)
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.Default(::std::nullopt);
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}
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::std::optional<LoadTemporalHint> symbolizeLoadTemporalHint(uint32_t value) {
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switch (value) {
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case 0: return LoadTemporalHint::RT;
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case 1: return LoadTemporalHint::NT;
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case 2: return LoadTemporalHint::HT;
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case 3: return LoadTemporalHint::LU;
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case 4: return LoadTemporalHint::NT_RT;
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case 5: return LoadTemporalHint::RT_NT;
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case 6: return LoadTemporalHint::NT_HT;
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default: return ::std::nullopt;
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}
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}
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} // namespace mlir::amdgpu
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