Implement generic MAX2771 raw Ethernet recorder

2026-08-01 01:15:47 +03:00
commit 79d07fdda7
57 changed files with 4810 additions and 0 deletions
@@ -0,0 +1,25 @@
+# FPGA/simulator generated directories
+.Xil/
+build/
+build_selftest/
+targets/*/build/
+targets/*/build_selftest/
+
+# Generated binaries and FPGA images
+host/max2771_raw_rx
+*.bit
+*.hex
+*.dcp
+
+# Tool logs/reports outside build directories
+reports/
+transcript
+clockInfo.txt
+vivado*.jou
+vivado*.log
+vivado*.str
+vsim.wlf
+
+# Local capture artifacts
+*.bin
+*.bin.log