Implement generic MAX2771 raw Ethernet recorder

docs/timing_constraints.md

@@ -0,0 +1,24 @@
+# Timing constraints index
+
+The authoritative target timing notes are:
+
+- [Genesys 2 timing constraints](../targets/genesys2/docs/timing_constraints.md)
+- [Efinix timing/build notes](../targets/efinix_ti375_c529/docs/efinity_flow.md)
+
+Both implementations constrain the RF clock to 30.547 ns by default and the
+Ethernet GMII domain to 8.000 ns. Their generated 125 MHz RGMII transmit clock
+phase and board-specific I/O timing are created in the corresponding target
+clock/periphery implementation.
+
+Only known asynchronous relationships and synchronizer/Gray-pointer CDC paths
+are treated as asynchronous. The design does not apply a broad false path from
+RF capture to Ethernet logic; the handwritten asynchronous FIFO is the explicit
+boundary. Unknown MAX2771 external input delays remain documented measurement
+requirements rather than invented constraints.
+
+Clean builds checked on 1 August 2026 reported:
+
+| Target | Setup slack | Hold slack | CDC |
+|---|---:|---:|---|
+| Genesys 2, Vivado 2026.1 | +0.212 ns worst | +0.090 ns worst | no unexpected major warning accepted by build script |
+| Ti375 C529, Efinity 2026.1 | +0.636 ns Ethernet, +25.614 ns RF | +0.094 ns Ethernet, +0.031 ns RF | no synchronizer warnings |