Implement generic MAX2771 raw Ethernet recorder

scripts/build_vivado.tcl

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+# Compatibility entry point retained for the documented repository-root path.
+# The only Genesys 2 implementation lives with its target-specific sources.
+set compatibility_dir [file normalize [file dirname [info script]]]
+source [file normalize [file join $compatibility_dir .. targets genesys2 scripts build_vivado.tcl]]

scripts/program_fpga.tcl

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+# Compatibility entry point retained for the documented repository-root path.
+# argv/tclargs are intentionally left unchanged for the target script.
+set compatibility_dir [file normalize [file dirname [info script]]]
+source [file normalize [file join $compatibility_dir .. targets genesys2 scripts program_fpga.tcl]]

scripts/run_common_sim.sh

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+#!/usr/bin/env bash
+set -euo pipefail
+
+repo_dir=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
+sim_dir="$repo_dir/build/common/questa"
+mkdir -p "$sim_dir"
+if [[ -d "$sim_dir/work" ]]; then
+    vdel -lib "$sim_dir/work" -all >/dev/null
+fi
+vlib "$sim_dir/work"
+
+vlog -work "$sim_dir/work" -sv \
+    "$repo_dir/rtl/common/async_fifo_gray.sv" \
+    "$repo_dir/rtl/common/max2771_capture.sv" \
+    "$repo_dir/rtl/common/ethernet_crc32.sv" \
+    "$repo_dir/rtl/common/ethernet_packetizer.sv" \
+    "$repo_dir/rtl/common/ethernet_tx_mac.sv" \
+    "$repo_dir/tb/common/tb_ethernet_crc32.sv" \
+    "$repo_dir/tb/common/tb_ethernet_tx_mac.sv" \
+    "$repo_dir/tb/common/tb_async_fifo_gray.sv" \
+    "$repo_dir/tb/common/tb_recorder_stream.sv" \
+    "$repo_dir/tb/common/tb_capture_overflow.sv"
+
+for test in tb_ethernet_crc32 tb_ethernet_tx_mac tb_async_fifo_gray \
+            tb_recorder_stream tb_capture_overflow; do
+    echo "== $test =="
+    vsim -c -lib "$sim_dir/work" "$test" -do 'run -all; quit -f'
+done