Implement generic MAX2771 raw Ethernet recorder

targets/efinix_ti375_c529/constraints/ti375_max2771_recorder.sdc

@@ -0,0 +1,26 @@
+# Core timing constraints for the Ti375 C529 target. The Efinity-generated
+# outflow/ti375_max2771_recorder.pt.sdc is prepended by build_efinity.sh and
+# contains the periphery clock constraints.
+
+# The external 100 MHz Ethernet reference, its PLL outputs, and the direct
+# 32.736 MHz GPIOR_95_CLK12 input are constrained in the generated periphery
+# SDC. Their core-side net names include eth_clk and rf_clk_pmod; no duplicate
+# create_clock is added here.
+
+# MAX2771 sampling is source-synchronous but exact clock-to-data plus board
+# skew is not supplied by the MAX2771 connection specification. Do not invent
+# set_input_delay numbers. Add measured/datasheet-derived -min and -max values
+# here before claiming external I/O timing closure, for example:
+# set_input_delay -clock rf_clk_pmod -max <MEASURED_MAX_NS> [get_ports {rf_data_pmod[*]}]
+# set_input_delay -clock rf_clk_pmod -min <MEASURED_MIN_NS> [get_ports {rf_data_pmod[*]}]
+
+# Only the RF and Ethernet clocks are asynchronous. FIFO Gray-pointer
+# synchronizers, the Gray counter synchronizer and pulse synchronizer are the
+# deliberate CDC paths. No functional RF-to-Ethernet combinational path exists.
+set_clock_groups -asynchronous \
+    -group [get_clocks {rf_clk_pmod}] \
+    -group [get_clocks {eth_clk eth_clk90 pll_dummy_clk}]
+
+# Efinity's async_reg attribute keeps the two synchronizer stages adjacent.
+# The RTL also limits CDC to Gray-coded pointers/counters or single-bit toggles;
+# no blanket false path is applied to unrelated logic.