Implement generic MAX2771 raw Ethernet recorder
This commit is contained in:
onur
+75
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#!/usr/bin/env bash
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set -euo pipefail
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target_dir=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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build_dir=${EFINIX_BUILD_DIR:-"$target_dir/build"}
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project=${EFINITY_PROJECT:-ti375_max2771_recorder}
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constraint_file=${EFINITY_CONSTRAINT_FILE:-"$target_dir/constraints/ti375_max2771_recorder.sdc"}
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if [[ -z ${EFINITY_HOME:-} ]]; then
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echo "ERROR: set EFINITY_HOME to the Efinity installation directory" >&2
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echo "Example: export EFINITY_HOME=/opt/efinity/2025.2" >&2
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exit 2
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fi
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if [[ ! -f "$EFINITY_HOME/bin/setup.sh" ]]; then
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echo "ERROR: $EFINITY_HOME/bin/setup.sh not found" >&2
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exit 2
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fi
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# shellcheck disable=SC1090
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export PYTHONPATH=${PYTHONPATH:-}
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source "$EFINITY_HOME/bin/setup.sh"
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mkdir -p "$build_dir"
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export EFINITY_BUILD_DIR="$build_dir"
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export EFINITY_PROJECT="$project"
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export EFINIX_DEVICE=${EFINIX_DEVICE:-Ti375C529}
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export EFINIX_TIMING_MODEL=${EFINIX_TIMING_MODEL:-C4}
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rf_clock_period_ns=${RF_CLOCK_PERIOD_NS:-30.547}
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if [[ ! $rf_clock_period_ns =~ ^[0-9]+([.][0-9]+)?$ ]]; then
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echo "ERROR: RF_CLOCK_PERIOD_NS must be a positive numeric period in ns" >&2
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exit 2
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fi
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cd "$build_dir"
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"$EFINITY_HOME/bin/python3" "$target_dir/scripts/generate_project.py"
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"$EFINITY_HOME/bin/python3" "$target_dir/interface/create_interface.py"
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pt_sdc="$build_dir/outflow/$project.pt.sdc"
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if [[ ! -f "$pt_sdc" ]]; then
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echo "ERROR: Interface Designer did not generate $pt_sdc" >&2
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exit 1
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fi
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{
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# A direct GCLK input has no frequency property in Interface Designer, so
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# Efinity emits this documented placeholder for the user clock period.
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sed "s/<USER_PERIOD>/$rf_clock_period_ns/g" "$pt_sdc"
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sed -n '1,$p' "$constraint_file"
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} > "$build_dir/${project}_merged.sdc"
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if grep -q '<USER_PERIOD>' "$build_dir/${project}_merged.sdc"; then
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echo "ERROR: unresolved RF input-clock period in merged SDC" >&2
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exit 1
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fi
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"$EFINITY_HOME/bin/python3" "$EFINITY_HOME/scripts/efx_run.py" \
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"$build_dir/$project.xml" --flow compile
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"$EFINITY_HOME/bin/python3" "$target_dir/scripts/check_timing.py" \
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"$build_dir/outflow/$project.timing.rpt"
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cdc_report="$build_dir/outflow/$project.cdc.rpt"
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if [[ ! -f "$cdc_report" ]] || ! grep -q "No Synchronizer warnings to report" "$cdc_report"; then
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echo "ERROR: Efinity CDC/synchronizer report is absent or contains warnings" >&2
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exit 1
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fi
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if grep -Eq "No ports matched|No clocks matched|No valid pin\(s\) found for clock" \
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"$build_dir/outflow/$project.log"; then
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echo "ERROR: major SDC coverage warning found in Efinity log" >&2
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exit 1
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fi
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if [[ ! -f "$build_dir/outflow/$project.bit" ]]; then
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echo "ERROR: expected JTAG bitstream was not generated" >&2
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exit 1
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fi
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echo "Bitstream: $build_dir/outflow/$project.bit"
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@@ -0,0 +1,8 @@
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#!/usr/bin/env bash
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set -euo pipefail
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target_dir=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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export EFINITY_PROJECT=ti375_ethernet_selftest
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export EFINITY_TOP=ti375_ethernet_selftest_top
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export EFINITY_BUILD_DIR=${EFINITY_SELFTEST_BUILD_DIR:-"$target_dir/build_selftest"}
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exec "$target_dir/scripts/build_efinity.sh"
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+35
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#!/usr/bin/env python3
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"""Fail conservatively on Efinity timing violations or absent clock coverage."""
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import re
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import sys
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from pathlib import Path
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if len(sys.argv) != 2:
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raise SystemExit("usage: check_timing.py OUTflow/project.timing.rpt")
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path = Path(sys.argv[1])
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if not path.is_file():
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raise SystemExit(f"timing report not found: {path}")
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text = path.read_text(encoding="utf-8", errors="replace")
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if re.search(r"\b(?:VIOLATED|timing\s+not\s+met|negative\s+slack)\b", text, re.I):
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raise SystemExit(f"timing violation reported in {path}")
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lower = text.lower()
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start = lower.find("clock relationship summary")
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if start < 0:
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raise SystemExit("Clock Relationship Summary is absent; cannot prove timing closure")
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end_candidates = [x for x in (
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lower.find("path details", start + 1),
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lower.find("max critical", start + 1),
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) if x >= 0]
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summary = text[start:min(end_candidates) if end_candidates else len(text)]
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# Relationship rows contain the setup/hold slack values. Reject any negative
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# decimal in this summary; clock names on this design contain no negative nums.
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if re.search(r"(?<![A-Za-z0-9_])-\d+(?:\.\d+)?", summary):
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raise SystemExit("negative setup/hold slack in Clock Relationship Summary")
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for required in ("eth_clk", "rf_clk_pmod"):
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if required not in text:
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raise SystemExit(f"required clock {required!r} is absent from timing report")
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print(f"Timing report accepted: {path}")
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+101
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#!/usr/bin/env python3
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"""Generate an Efinity project XML without a GUI/project database dependency."""
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import datetime
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import os
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from pathlib import Path
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import xml.dom.minidom
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import xml.etree.ElementTree as ET
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TARGET = Path(__file__).resolve().parents[1]
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ROOT = TARGET.parents[1]
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BUILD = Path(os.environ.get("EFINIX_BUILD_DIR", TARGET / "build")).resolve()
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PROJECT = os.environ.get("EFINITY_PROJECT", "ti375_max2771_recorder")
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TOP = os.environ.get("EFINITY_TOP", "ti375_max2771_recorder_top")
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DEVICE = os.environ.get("EFINIX_DEVICE", "Ti375C529")
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TIMING_MODEL = os.environ.get("EFINIX_TIMING_MODEL", "C4")
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EFINITY_HOME = Path(os.environ["EFINITY_HOME"]).resolve()
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version_file = EFINITY_HOME / "scripts" / "sw_version.txt"
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SW_VERSION = version_file.read_text(encoding="utf-8").splitlines()[0].strip()
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sources = [
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ROOT / "rtl" / "common" / "reset_sync.sv",
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ROOT / "rtl" / "common" / "pulse_sync.sv",
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ROOT / "rtl" / "common" / "gray_counter_sync.sv",
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ROOT / "rtl" / "common" / "async_fifo_gray.sv",
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ROOT / "rtl" / "common" / "max2771_capture.sv",
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ROOT / "rtl" / "common" / "ethernet_crc32.sv",
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ROOT / "rtl" / "common" / "ethernet_packetizer.sv",
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ROOT / "rtl" / "common" / "ethernet_tx_mac.sv",
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ROOT / "rtl" / "common" / "phy_reset_ctrl.sv",
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ROOT / "rtl" / "common" / "mdio_master.sv",
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TARGET / "rtl" / "phy_init_rtl8211f.sv",
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TARGET / "rtl" / "rgmii_tx_efinix.sv",
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TARGET / "rtl" / "ti375_max2771_recorder_top.sv",
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TARGET / "rtl" / "ti375_ethernet_selftest_top.sv",
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]
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for source in sources:
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if not source.is_file():
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raise SystemExit(f"missing RTL source: {source}")
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ns = "http://www.efinixinc.com/enf_proj"
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root = ET.Element("efx:project", {
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"xmlns:efx": ns,
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"name": PROJECT,
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"location": str(BUILD),
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"sw_version": SW_VERSION,
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"last_change_date": "Date : " + datetime.datetime.now().strftime("%Y-%m-%d %H:%M"),
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})
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device_info = ET.SubElement(root, "efx:device_info")
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ET.SubElement(device_info, "efx:family", name="Titanium")
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ET.SubElement(device_info, "efx:device", name=DEVICE)
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ET.SubElement(device_info, "efx:timing_model", name=TIMING_MODEL)
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design_info = ET.SubElement(root, "efx:design_info", {
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"def_veri_version": "verilog_2k", "def_vhdl_version": "vhdl_2008"
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})
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ET.SubElement(design_info, "efx:top_module", name=TOP)
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for source in sources:
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ET.SubElement(design_info, "efx:design_file", {
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"name": str(source), "version": "default", "library": "default"
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})
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constraint_info = ET.SubElement(root, "efx:constraint_info")
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ET.SubElement(constraint_info, "efx:sdc_file", name=str(BUILD / f"{PROJECT}_merged.sdc"))
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ET.SubElement(root, "efx:misc_info")
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ET.SubElement(root, "efx:ip_info")
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def add_param(parent, name, value, value_type="e_string"):
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ET.SubElement(parent, "efx:param", name=name, value=str(value), value_type=value_type)
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synth = ET.SubElement(root, "efx:synthesis", tool_name="efx_map")
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add_param(synth, "work_dir", "work_syn")
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add_param(synth, "mode", "speed", "e_option")
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add_param(synth, "infer-clk-enable", "3", "e_option")
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add_param(synth, "infer-sync-set-reset", "1", "e_option")
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add_param(synth, "bram_output_regs_packing", "1", "e_option")
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add_param(synth, "retiming", "1", "e_option")
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add_param(synth, "seq_opt", "1", "e_option")
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pnr = ET.SubElement(root, "efx:place_and_route", tool_name="efx_pnr")
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add_param(pnr, "work_dir", "work_pnr")
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pgm = ET.SubElement(root, "efx:bitstream_generation", tool_name="efx_pgm")
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add_param(pgm, "mode", "active", "e_string")
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add_param(pgm, "width", "1", "e_string")
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add_param(pgm, "oscillator_clock_divider", "DIV8", "e_option")
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add_param(pgm, "spi_low_power_mode", "on", "e_bool")
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add_param(pgm, "io_weak_pullup", "on", "e_bool")
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add_param(pgm, "enable_roms", "smart", "e_option")
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add_param(pgm, "bitstream_compression", "on", "e_bool")
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add_param(pgm, "generate_bit", "on", "e_bool")
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add_param(pgm, "generate_hex", "on", "e_bool")
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ET.SubElement(root, "efx:debugger")
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ET.SubElement(root, "efx:security")
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BUILD.mkdir(parents=True, exist_ok=True)
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raw = ET.tostring(root, encoding="utf-8")
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pretty = xml.dom.minidom.parseString(raw).toprettyxml(indent=" ")
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(BUILD / f"{PROJECT}.xml").write_text(pretty, encoding="utf-8")
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print(BUILD / f"{PROJECT}.xml")
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+21
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#!/usr/bin/env bash
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set -euo pipefail
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target_dir=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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build_dir=${EFINITY_BUILD_DIR:-"$target_dir/build"}
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project=${EFINITY_PROJECT:-ti375_max2771_recorder}
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if [[ -z ${EFINITY_HOME:-} || ! -f "$EFINITY_HOME/bin/setup.sh" ]]; then
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echo "ERROR: set EFINITY_HOME to a valid Efinity installation" >&2
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exit 2
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fi
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# shellcheck disable=SC1090
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export PYTHONPATH=${PYTHONPATH:-}
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source "$EFINITY_HOME/bin/setup.sh"
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if [[ ! -f "$build_dir/outflow/$project.bit" ]]; then
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echo "ERROR: build first; bitstream is absent" >&2
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exit 1
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fi
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cd "$build_dir"
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"$EFINITY_HOME/bin/python3" "$EFINITY_HOME/scripts/efx_run.py" \
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"$build_dir/$project.xml" --flow program --pgm_opts mode=jtag
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@@ -0,0 +1,7 @@
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#!/usr/bin/env bash
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set -euo pipefail
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target_dir=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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export EFINITY_PROJECT=ti375_ethernet_selftest
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export EFINITY_BUILD_DIR=${EFINITY_SELFTEST_BUILD_DIR:-"$target_dir/build_selftest"}
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exec "$target_dir/scripts/program_efinity.sh"
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Executable
+36
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#!/usr/bin/env bash
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set -euo pipefail
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target_dir=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
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repo_dir=$(cd "$target_dir/../.." && pwd)
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sim_dir="$target_dir/build/questa"
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mkdir -p "$sim_dir"
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if [[ -d "$sim_dir/work" ]]; then
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vdel -lib "$sim_dir/work" -all >/dev/null
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fi
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vlib "$sim_dir/work"
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vlog -work "$sim_dir/work" -sv \
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"$repo_dir/rtl/common/reset_sync.sv" \
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"$repo_dir/rtl/common/pulse_sync.sv" \
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"$repo_dir/rtl/common/gray_counter_sync.sv" \
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"$repo_dir/rtl/common/async_fifo_gray.sv" \
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"$repo_dir/rtl/common/max2771_capture.sv" \
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"$repo_dir/rtl/common/ethernet_crc32.sv" \
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"$repo_dir/rtl/common/ethernet_packetizer.sv" \
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"$repo_dir/rtl/common/ethernet_tx_mac.sv" \
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"$repo_dir/rtl/common/phy_reset_ctrl.sv" \
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"$repo_dir/rtl/common/mdio_master.sv" \
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"$target_dir/rtl/phy_init_rtl8211f.sv" \
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"$target_dir/rtl/rgmii_tx_efinix.sv" \
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"$target_dir/rtl/ti375_max2771_recorder_top.sv" \
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"$target_dir/tb/tb_rgmii_tx_efinix.sv" \
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"$target_dir/tb/tb_phy_init_rtl8211f.sv"
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for test in tb_rgmii_tx_efinix tb_phy_init_rtl8211f; do
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echo "== $test =="
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vsim -c -lib "$sim_dir/work" "$test" -do 'run -all; quit -f'
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done
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echo "Efinix target unit tests passed. Running the shared recorder regression..."
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"$repo_dir/scripts/run_common_sim.sh"
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