Implement generic MAX2771 raw Ethernet recorder

targets/genesys2/scripts/build_vivado.tcl

@@ -0,0 +1,93 @@
+# Non-project Vivado build for the Genesys 2 MAX2771 recorder.
+# Run from repository root:
+# vivado -mode batch -source targets/genesys2/scripts/build_vivado.tcl
+
+set script_dir [file normalize [file dirname [info script]]]
+set target_dir [file normalize [file join $script_dir ..]]
+set root_dir   [file normalize [file join $target_dir .. ..]]
+set build_dir  [file join $root_dir build genesys2 vivado]
+set report_dir [file join $root_dir build genesys2 reports]
+file mkdir $build_dir
+file mkdir $report_dir
+
+set part xc7k325tffg900-2
+set top  max2771_recorder_top
+create_project -in_memory -part $part
+set_property target_language Verilog [current_project]
+set_property default_lib work [current_project]
+set_property verilog_define {SYNTHESIS=1} [current_fileset]
+
+set common_rtl [lsort [glob -nocomplain [file join $root_dir rtl common *.sv]]]
+set target_rtl [lsort [glob -nocomplain [file join $target_dir rtl *.sv]]]
+set rtl_files [concat $common_rtl $target_rtl]
+if {[llength $rtl_files] == 0} { error "No RTL files found" }
+read_verilog -sv $rtl_files
+read_xdc [file join $target_dir constraints genesys2_max2771_recorder.xdc]
+
+synth_design -top $top -part $part -flatten_hierarchy rebuilt
+write_checkpoint -force [file join $build_dir post_synth.dcp]
+report_utilization -file [file join $report_dir post_synth_utilization.rpt]
+report_clocks -file [file join $report_dir clocks.rpt]
+report_clock_utilization -file [file join $report_dir clock_utilization.rpt]
+check_timing -verbose -file [file join $report_dir check_timing_post_synth.rpt]
+report_cdc -details -file [file join $report_dir cdc_post_synth.rpt]
+
+# Fail for registers lacking a clock. I/O delay omissions are separately and
+# deliberately documented because the MAX2771 tCO/board skew is not yet known.
+set no_clock_text [check_timing -override_defaults no_clock -return_string]
+if {[regexp -nocase {([1-9][0-9]*) register[^\n]*no clock} $no_clock_text]} {
+    error "Unconstrained sequential clocks detected; see check_timing_post_synth.rpt"
+}
+
+# Vivado exposes CDC violations as objects after report_cdc. Any Critical or
+# Warning CDC not waived by structural ASYNC_REG recognition stops the build.
+if {[llength [info commands get_cdc_violations]] != 0} {
+    set major_cdc [get_cdc_violations -quiet -filter {SEVERITY == "Critical" || SEVERITY == "Warning"}]
+    set unexpected_cdc 0
+    foreach violation $major_cdc {
+        # CDC-6 is Vivado's expected classification for a multi-bit Gray bus
+        # whose first two destination stages carry ASYNC_REG. Only the three
+        # named Gray synchronizers are accepted; every other warning is fatal.
+        set description [report_property -return_string $violation]
+        if {![regexp {u_sample_fifo/(wgray_rsync1|rgray_wsync1)|u_drop_sync/gray_sync1} $description]} {
+            puts stderr "Unexpected CDC violation:\n$description"
+            set unexpected_cdc 1
+        }
+    }
+    if {$unexpected_cdc} { error "Major unexpected CDC warnings detected; see cdc_post_synth.rpt" }
+}
+
+opt_design
+place_design
+phys_opt_design
+write_checkpoint -force [file join $build_dir post_place.dcp]
+report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose \
+    -file [file join $report_dir timing_post_place.rpt]
+
+route_design
+phys_opt_design
+write_checkpoint -force [file join $build_dir post_route.dcp]
+report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose \
+    -file [file join $report_dir timing_post_route.rpt]
+report_timing -delay_type max -max_paths 50 -sort_by group \
+    -file [file join $report_dir setup_paths.rpt]
+report_timing -delay_type min -max_paths 50 -sort_by group \
+    -file [file join $report_dir hold_paths.rpt]
+report_utilization -hierarchical -file [file join $report_dir utilization_post_route.rpt]
+report_methodology -file [file join $report_dir methodology_post_route.rpt]
+report_drc -file [file join $report_dir drc_post_route.rpt]
+
+set setup_paths [get_timing_paths -quiet -delay_type max -max_paths 1]
+set hold_paths  [get_timing_paths -quiet -delay_type min -max_paths 1]
+if {[llength $setup_paths] == 0 || [llength $hold_paths] == 0} {
+    error "Timing paths unavailable; clocks may be unconstrained"
+}
+set setup_slack [get_property SLACK [lindex $setup_paths 0]]
+set hold_slack  [get_property SLACK [lindex $hold_paths 0]]
+if {$setup_slack < 0.0 || $hold_slack < 0.0} {
+    error "Timing failed: setup WNS=$setup_slack ns, hold WNS=$hold_slack ns"
+}
+
+write_bitstream -force [file join $build_dir max2771_recorder.bit]
+puts "BUILD PASSED: setup WNS=$setup_slack ns, hold WNS=$hold_slack ns"
+puts "Bitstream: [file join $build_dir max2771_recorder.bit]"

targets/genesys2/scripts/program_fpga.tcl

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+# Run: vivado -mode batch -source targets/genesys2/scripts/program_fpga.tcl -tclargs [bitstream]
+set script_dir [file normalize [file dirname [info script]]]
+set target_dir [file normalize [file join $script_dir ..]]
+set root_dir [file normalize [file join $target_dir .. ..]]
+if {$argc > 0} {
+    set bitstream [file normalize [lindex $argv 0]]
+} else {
+    set bitstream [file join $root_dir build genesys2 vivado max2771_recorder.bit]
+}
+if {![file exists $bitstream]} { error "Bitstream not found: $bitstream" }
+
+open_hw_manager
+connect_hw_server
+open_hw_target
+set devices [get_hw_devices -quiet -filter {PART =~ "xc7k325t*"}]
+if {[llength $devices] == 0} { error "No xc7k325t JTAG device found" }
+set device [lindex $devices 0]
+current_hw_device $device
+refresh_hw_device -update_hw_probes false $device
+set_property PROGRAM.FILE $bitstream $device
+program_hw_devices $device
+refresh_hw_device $device
+puts "Programmed $device with $bitstream"
+close_hw_manager