# FPGA/simulator generated directories
.Xil/
build/
build_selftest/
targets/*/build/
targets/*/build_selftest/

# Generated binaries and FPGA images
host/max2771_raw_rx
*.bit
*.hex
*.dcp

# Tool logs/reports outside build directories
reports/
transcript
clockInfo.txt
vivado*.jou
vivado*.log
vivado*.str
vsim.wlf

# Local capture artifacts
*.bin
*.bin.log