`default_nettype none

module phy_reset_ctrl #(
    parameter int unsigned CLK_HZ = 125_000_000,
    parameter int unsigned RESET_LOW_MS = 10
) (
    input  wire logic clk,
    input  wire logic rst,
    output      logic phy_reset_n,
    output      logic reset_complete
);
    localparam longint unsigned RESET_CYCLES = (CLK_HZ / 1000) * RESET_LOW_MS;
    localparam int unsigned COUNT_W = (RESET_CYCLES < 2) ? 1 : $clog2(RESET_CYCLES + 1);
    logic [COUNT_W-1:0] count;

    always_ff @(posedge clk) begin
        if (rst) begin
            phy_reset_n   <= 1'b0;
            reset_complete <= 1'b0;
            count <= '0;
        end else if (!reset_complete) begin
            phy_reset_n <= 1'b0;
            if (count == RESET_CYCLES-1) begin
                phy_reset_n    <= 1'b1;
                reset_complete <= 1'b1;
            end else count <= count + {{(COUNT_W-1){1'b0}},1'b1};
        end else begin
            phy_reset_n <= 1'b1;
        end
    end
endmodule

`default_nettype wire