`default_nettype none

// Toggle-based pulse crossing. Pulses must be separated by at least two
// destination clock cycles. Assertion is asynchronous only at the synchronizer.
module pulse_sync (
    input  wire logic src_clk,
    input  wire logic src_rst,
    input  wire logic src_pulse,
    input  wire logic dst_clk,
    input  wire logic dst_rst,
    output      logic dst_pulse
);
    logic src_toggle;
    (* ASYNC_REG = "TRUE" *) logic dst_sync1;
    (* ASYNC_REG = "TRUE" *) logic dst_sync2;
    logic dst_sync2_d;

    always_ff @(posedge src_clk) begin
        if (src_rst) src_toggle <= 1'b0;
        else if (src_pulse) src_toggle <= ~src_toggle;
    end

    always_ff @(posedge dst_clk) begin
        if (dst_rst) begin
            dst_sync1   <= 1'b0;
            dst_sync2   <= 1'b0;
            dst_sync2_d <= 1'b0;
            dst_pulse   <= 1'b0;
        end else begin
            dst_sync1   <= src_toggle;
            dst_sync2   <= dst_sync1;
            dst_sync2_d <= dst_sync2;
            dst_pulse   <= dst_sync2 ^ dst_sync2_d;
        end
    end
endmodule

`default_nettype wire