# Hardware assumptions index

Board-specific facts and assumptions are kept beside the target that uses them:

- [Genesys 2 hardware assumptions](../targets/genesys2/docs/hardware_assumptions.md)
- [Efinix Ti375 C529 hardware assumptions](../targets/efinix_ti375_c529/docs/hardware_assumptions.md)

The following items are shared assumptions from the recorder specification:

- the MAX2771 produces one literal 4-bit word on every selected RF clock edge;
- nominal maximum RF clock frequency is 32.736 MHz;
- the default capture edge is rising and the default packing puts the earlier
  sample in the high nibble;
- the source cannot be backpressured.

The following are deliberately **not** claimed as verified:

- MAX2771 clock-to-data minimum and maximum delays at the connector;
- RF cable/adapter clock-to-data skew and signal integrity;
- a loss-free sample-zero boundary when RF capture starts before Gigabit link;
- timing behavior outside the FPGA speed/temperature model selected by each
  target build.

Obtain the MAX2771 timing values from the exact device/mode datasheet and
measure the assembled clock/data path before final board-level timing sign-off.
No arbitrary `set_input_delay` is presented as a measured value.