`default_nettype none

module reset_sync #(
    parameter int unsigned STAGES = 2
) (
    input  wire logic clk,
    input  wire logic arst,
    output      logic srst
);
    (* ASYNC_REG = "TRUE" *) logic [STAGES-1:0] sync_ff;

    initial begin
        if (STAGES < 2) $error("reset_sync STAGES must be at least two");
    end

    always_ff @(posedge clk or posedge arst) begin
        if (arst) begin
            sync_ff <= '1;
        end else begin
            sync_ff <= {sync_ff[STAGES-2:0], 1'b0};
        end
    end

    assign srst = sync_ff[STAGES-1];
endmodule

`default_nettype wire