onur
123 lines
4.7 KiB
Systemverilog
123 lines
4.7 KiB
Systemverilog
`default_nettype none
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// Handwritten dual-clock FIFO. Only Gray pointers cross clock domains. Memory
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// writes occur in w_clk and the read data is registered in r_clk, allowing BRAM
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// inference without a combinational CDC path.
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module async_fifo_gray #(
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parameter int unsigned DATA_WIDTH = 69,
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parameter int unsigned DEPTH = 16384
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) (
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input wire logic w_clk,
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input wire logic w_rst,
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input wire logic w_en,
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input wire logic [DATA_WIDTH-1:0] w_data,
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output logic w_full,
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output logic [$clog2(DEPTH):0] w_level,
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output logic [63:0] overflow_attempt_count,
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input wire logic r_clk,
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input wire logic r_rst,
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input wire logic r_en,
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output logic [DATA_WIDTH-1:0] r_data,
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output logic r_valid,
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output logic r_empty,
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output logic [$clog2(DEPTH):0] r_level,
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output logic [63:0] underflow_attempt_count
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);
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localparam int unsigned ADDR_WIDTH = $clog2(DEPTH);
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localparam int unsigned PTR_WIDTH = ADDR_WIDTH + 1;
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(* ram_style = "block" *) logic [DATA_WIDTH-1:0] mem [0:DEPTH-1];
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logic [PTR_WIDTH-1:0] wbin, wgray, rbin, rgray;
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logic [PTR_WIDTH-1:0] wbin_next, wgray_next;
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logic [PTR_WIDTH-1:0] rbin_next, rgray_next;
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(* ASYNC_REG = "TRUE" *) logic [PTR_WIDTH-1:0] rgray_wsync1, rgray_wsync2;
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(* ASYNC_REG = "TRUE" *) logic [PTR_WIDTH-1:0] wgray_rsync1, wgray_rsync2;
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logic [PTR_WIDTH-1:0] rbin_wsync, wbin_rsync;
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logic [DATA_WIDTH-1:0] r_mem_data;
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logic w_push, r_pop;
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integer i;
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initial begin
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if (DEPTH < 4 || (DEPTH & (DEPTH-1)) != 0)
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$error("async_fifo_gray DEPTH must be a power of two >= 4");
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if (DATA_WIDTH == 0) $error("async_fifo_gray DATA_WIDTH must be nonzero");
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end
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assign w_push = w_en && !w_full;
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assign r_pop = r_en && !r_empty;
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assign r_data = r_valid ? r_mem_data : {DATA_WIDTH{1'b0}};
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assign wbin_next = wbin + {{(PTR_WIDTH-1){1'b0}}, w_push};
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assign rbin_next = rbin + {{(PTR_WIDTH-1){1'b0}}, r_pop};
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assign wgray_next = (wbin_next >> 1) ^ wbin_next;
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assign rgray_next = (rbin_next >> 1) ^ rbin_next;
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always_comb begin
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rbin_wsync[PTR_WIDTH-1] = rgray_wsync2[PTR_WIDTH-1];
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wbin_rsync[PTR_WIDTH-1] = wgray_rsync2[PTR_WIDTH-1];
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for (i = PTR_WIDTH-2; i >= 0; i = i - 1) begin
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rbin_wsync[i] = rbin_wsync[i+1] ^ rgray_wsync2[i];
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wbin_rsync[i] = wbin_rsync[i+1] ^ wgray_rsync2[i];
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end
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end
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always_comb begin
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w_level = wbin - rbin_wsync;
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r_level = wbin_rsync - rbin;
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end
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always_ff @(posedge w_clk or posedge w_rst) begin
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if (w_rst) begin
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wbin <= '0;
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wgray <= '0;
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w_full <= 1'b0;
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rgray_wsync1 <= '0;
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rgray_wsync2 <= '0;
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overflow_attempt_count <= 64'd0;
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end else begin
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rgray_wsync1 <= rgray;
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rgray_wsync2 <= rgray_wsync1;
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if (w_en && w_full)
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overflow_attempt_count <= overflow_attempt_count + 64'd1;
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wbin <= wbin_next;
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wgray <= wgray_next;
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// Invert the two most-significant synchronized read-pointer bits.
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w_full <= (wgray_next == {~rgray_wsync2[PTR_WIDTH-1:PTR_WIDTH-2],
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rgray_wsync2[PTR_WIDTH-3:0]});
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end
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end
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always_ff @(posedge r_clk or posedge r_rst) begin
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if (r_rst) begin
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rbin <= '0;
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rgray <= '0;
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r_valid <= 1'b0;
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r_empty <= 1'b1;
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wgray_rsync1 <= '0;
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wgray_rsync2 <= '0;
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underflow_attempt_count <= 64'd0;
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end else begin
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wgray_rsync1 <= wgray;
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wgray_rsync2 <= wgray_rsync1;
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r_valid <= r_pop;
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if (r_en && r_empty)
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underflow_attempt_count <= underflow_attempt_count + 64'd1;
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rbin <= rbin_next;
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rgray <= rgray_next;
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r_empty <= (rgray_next == wgray_rsync2);
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end
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end
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// Keep memory access out of the asynchronously-reset pointer processes.
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// This is the supported true-dual-clock block-RAM inference template.
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always_ff @(posedge w_clk) begin
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if (w_push) mem[wbin[ADDR_WIDTH-1:0]] <= w_data;
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end
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always_ff @(posedge r_clk) begin
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if (r_pop) r_mem_data <= mem[rbin[ADDR_WIDTH-1:0]];
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end
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endmodule
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`default_nettype wire
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