onur
200 lines
7.8 KiB
Systemverilog
200 lines
7.8 KiB
Systemverilog
`default_nettype none
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module ethernet_tx_mac #(
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parameter logic [47:0] DEST_MAC = 48'hffffffffffff,
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parameter logic [47:0] SOURCE_MAC = 48'h022771000001,
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parameter logic [15:0] ETHERTYPE = 16'h88b5
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) (
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input wire logic clk,
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input wire logic rst,
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input wire logic frame_start,
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input wire logic [10:0] payload_length,
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input wire logic [7:0] payload_data,
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input wire logic payload_valid,
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output logic payload_ready,
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output logic [7:0] gmii_txd,
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output logic gmii_tx_en,
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output logic gmii_tx_er,
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output logic busy,
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output logic frame_done,
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output logic [63:0] frames_transmitted,
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output logic [63:0] payload_bytes_transmitted
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);
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typedef enum logic [3:0] {
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S_IDLE, S_PREAMBLE, S_SFD, S_DEST, S_SOURCE, S_TYPE,
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S_PAYLOAD, S_PAD, S_FCS, S_IFG
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} state_t;
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state_t state;
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logic [3:0] byte_count;
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logic [10:0] payload_len_q;
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logic [10:0] payload_count;
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logic [5:0] pad_remaining;
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logic [3:0] ifg_count;
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logic [31:0] crc_q;
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logic [31:0] crc_next;
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logic [31:0] fcs_q;
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logic [15:0] requested_body_length;
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ethernet_crc32 u_crc_next (
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.crc_in(crc_q), .data_in(gmii_txd), .crc_out(crc_next)
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);
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always_comb begin
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gmii_txd = 8'h00;
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gmii_tx_en = 1'b0;
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gmii_tx_er = 1'b0;
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payload_ready = 1'b0;
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busy = (state != S_IDLE);
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case (state)
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S_PREAMBLE: begin gmii_tx_en = 1'b1; gmii_txd = 8'h55; end
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S_SFD: begin gmii_tx_en = 1'b1; gmii_txd = 8'hd5; end
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S_DEST: begin
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gmii_tx_en = 1'b1;
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case (byte_count)
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4'd0: gmii_txd = DEST_MAC[47:40];
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4'd1: gmii_txd = DEST_MAC[39:32];
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4'd2: gmii_txd = DEST_MAC[31:24];
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4'd3: gmii_txd = DEST_MAC[23:16];
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4'd4: gmii_txd = DEST_MAC[15:8];
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default: gmii_txd = DEST_MAC[7:0];
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endcase
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end
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S_SOURCE: begin
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gmii_tx_en = 1'b1;
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case (byte_count)
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4'd0: gmii_txd = SOURCE_MAC[47:40];
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4'd1: gmii_txd = SOURCE_MAC[39:32];
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4'd2: gmii_txd = SOURCE_MAC[31:24];
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4'd3: gmii_txd = SOURCE_MAC[23:16];
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4'd4: gmii_txd = SOURCE_MAC[15:8];
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default: gmii_txd = SOURCE_MAC[7:0];
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endcase
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end
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S_TYPE: begin
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gmii_tx_en = 1'b1;
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gmii_txd = (byte_count == 4'd0) ? ETHERTYPE[15:8] : ETHERTYPE[7:0];
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end
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S_PAYLOAD: begin
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gmii_tx_en = 1'b1;
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payload_ready = 1'b1;
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gmii_txd = payload_data;
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end
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S_PAD: begin gmii_tx_en = 1'b1; gmii_txd = 8'h00; end
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S_FCS: begin
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gmii_tx_en = 1'b1;
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case (byte_count)
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4'd0: gmii_txd = fcs_q[7:0];
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4'd1: gmii_txd = fcs_q[15:8];
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4'd2: gmii_txd = fcs_q[23:16];
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default: gmii_txd = fcs_q[31:24];
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endcase
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end
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default: begin end
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endcase
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end
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always_comb requested_body_length = 16'd14 + {5'd0, payload_length};
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= S_IDLE;
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byte_count <= 4'd0;
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payload_len_q <= 11'd0;
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payload_count <= 11'd0;
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pad_remaining <= 6'd0;
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ifg_count <= 4'd0;
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crc_q <= 32'hffffffff;
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fcs_q <= 32'd0;
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frame_done <= 1'b0;
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frames_transmitted <= 64'd0;
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payload_bytes_transmitted <= 64'd0;
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end else begin
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frame_done <= 1'b0;
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case (state)
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S_IDLE: begin
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if (frame_start && payload_length <= 11'd1500) begin
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payload_len_q <= payload_length;
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payload_count <= 11'd0;
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byte_count <= 4'd0;
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crc_q <= 32'hffffffff;
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if (requested_body_length < 16'd60)
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pad_remaining <= 16'd60 - requested_body_length;
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else
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pad_remaining <= 6'd0;
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state <= S_PREAMBLE;
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end
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end
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S_PREAMBLE: begin
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if (byte_count == 4'd6) begin byte_count <= 4'd0; state <= S_SFD; end
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else byte_count <= byte_count + 4'd1;
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end
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S_SFD: begin byte_count <= 4'd0; state <= S_DEST; end
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S_DEST: begin
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crc_q <= crc_next;
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if (byte_count == 4'd5) begin byte_count <= 4'd0; state <= S_SOURCE; end
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else byte_count <= byte_count + 4'd1;
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end
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S_SOURCE: begin
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crc_q <= crc_next;
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if (byte_count == 4'd5) begin byte_count <= 4'd0; state <= S_TYPE; end
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else byte_count <= byte_count + 4'd1;
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end
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S_TYPE: begin
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crc_q <= crc_next;
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if (byte_count == 4'd1) begin
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byte_count <= 4'd0;
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if (payload_len_q != 11'd0) state <= S_PAYLOAD;
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else if (pad_remaining != 6'd0) state <= S_PAD;
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else begin fcs_q <= ~crc_next; state <= S_FCS; end
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end else byte_count <= 4'd1;
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end
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S_PAYLOAD: begin
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if (payload_valid) begin
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crc_q <= crc_next;
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payload_count <= payload_count + 11'd1;
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if (payload_count + 11'd1 == payload_len_q) begin
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if (pad_remaining != 6'd0) state <= S_PAD;
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else begin fcs_q <= ~crc_next; byte_count <= 4'd0; state <= S_FCS; end
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end
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end
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end
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S_PAD: begin
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crc_q <= crc_next;
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if (pad_remaining == 6'd1) begin
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pad_remaining <= 6'd0;
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fcs_q <= ~crc_next;
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byte_count <= 4'd0;
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state <= S_FCS;
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end else pad_remaining <= pad_remaining - 6'd1;
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end
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S_FCS: begin
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if (byte_count == 4'd3) begin byte_count <= 4'd0; ifg_count <= 4'd0; state <= S_IFG; end
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else byte_count <= byte_count + 4'd1;
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end
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S_IFG: begin
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if (ifg_count == 4'd11) begin
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ifg_count <= 4'd0;
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state <= S_IDLE;
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frame_done <= 1'b1;
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frames_transmitted <= frames_transmitted + 64'd1;
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payload_bytes_transmitted <= payload_bytes_transmitted + {53'd0, payload_len_q};
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end else ifg_count <= ifg_count + 4'd1;
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end
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default: state <= S_IDLE;
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endcase
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end
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end
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`ifndef SYNTHESIS
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// The packetizer preassembles every frame, so this contract must hold and
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// hardware never encodes TX_ER on RGMII.
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always_ff @(posedge clk) begin
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if (!rst && state == S_PAYLOAD && !payload_valid)
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$error("ethernet_tx_mac payload stream underflow");
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end
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`endif
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endmodule
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`default_nettype wire
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