onur
70 lines
2.6 KiB
Systemverilog
70 lines
2.6 KiB
Systemverilog
`default_nettype none
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module max2771_capture #(
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parameter bit CAPTURE_RISING = 1'b1
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) (
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input wire logic rf_clk_pmod,
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input wire logic rst,
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input wire logic [3:0] rf_data_pmod,
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input wire logic fifo_full,
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output wire logic fifo_w_clk,
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output wire logic fifo_w_en,
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output wire logic [68:0] fifo_w_data,
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output logic [63:0] samples_seen,
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output logic [63:0] samples_captured,
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output logic [63:0] samples_dropped,
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output logic loss_latched,
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output logic sample_activity_pulse
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);
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// The inversion selects the physical falling edge while retaining a single
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// positive-edge sequential implementation. Vivado maps clock inversion onto
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// the clocking resource; fifo_w_clk clocks both capture bookkeeping and FIFO.
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assign fifo_w_clk = CAPTURE_RISING ? rf_clk_pmod : ~rf_clk_pmod;
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(* IOB = "TRUE" *) logic [3:0] sample_iob;
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logic [63:0] sample_index_iob;
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logic sample_valid;
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logic discontinuity_pending;
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assign fifo_w_en = sample_valid;
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// Entry format: loss immediately before this sample, absolute index, nibble.
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assign fifo_w_data = {discontinuity_pending, sample_index_iob, sample_iob};
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always_ff @(posedge fifo_w_clk or posedge rst) begin
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if (rst) begin
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sample_iob <= 4'd0;
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sample_index_iob <= 64'd0;
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sample_valid <= 1'b0;
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discontinuity_pending <= 1'b0;
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samples_seen <= 64'd0;
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samples_captured <= 64'd0;
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samples_dropped <= 64'd0;
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loss_latched <= 1'b0;
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sample_activity_pulse <= 1'b0;
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end else begin
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// IOB input register: no combinational data path reaches the FIFO.
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sample_iob <= rf_data_pmod;
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sample_index_iob <= samples_seen;
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sample_valid <= 1'b1;
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samples_seen <= samples_seen + 64'd1;
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sample_activity_pulse <= 1'b0;
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if (samples_seen[15:0] == 16'hffff)
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sample_activity_pulse <= 1'b1;
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if (sample_valid) begin
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if (fifo_full) begin
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samples_dropped <= samples_dropped + 64'd1;
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discontinuity_pending <= 1'b1;
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loss_latched <= 1'b1;
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end else begin
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samples_captured <= samples_captured + 64'd1;
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discontinuity_pending <= 1'b0;
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end
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end
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end
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end
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endmodule
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`default_nettype wire
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