onur
98 lines
3.5 KiB
Systemverilog
98 lines
3.5 KiB
Systemverilog
`default_nettype none
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// IEEE 802.3 Clause-22 management interface. MDC is stopped low between
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// commands. A read releases MDIO for both turnaround bits and all data bits.
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module mdio_master #(
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parameter int unsigned MDC_DIV = 25
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) (
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input wire logic clk,
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input wire logic rst,
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input wire logic start,
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input wire logic command_write,
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input wire logic [4:0] phy_address,
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input wire logic [4:0] register_address,
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input wire logic [15:0] write_data,
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output logic busy,
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output logic done,
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output logic [15:0] read_data,
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output logic read_valid,
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output logic mdc,
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input wire logic mdio_i,
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output logic mdio_o,
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output logic mdio_oe
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);
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localparam int unsigned DIV_W = (MDC_DIV < 2) ? 1 : $clog2(MDC_DIV);
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logic [DIV_W-1:0] div_count;
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logic [5:0] bit_index;
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logic [63:0] frame_bits;
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logic [15:0] read_shift;
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logic read_command_q;
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initial begin
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if (MDC_DIV < 2) $error("MDC_DIV must be at least two");
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end
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always_comb begin
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mdio_o = frame_bits[bit_index];
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mdio_oe = busy;
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if (busy && read_command_q && bit_index <= 6'd17)
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mdio_oe = 1'b0;
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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busy <= 1'b0;
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done <= 1'b0;
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read_valid <= 1'b0;
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read_data <= 16'd0;
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read_shift <= 16'd0;
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mdc <= 1'b0;
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div_count <= '0;
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bit_index <= 6'd63;
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frame_bits <= 64'hffffffff_6000_0000;
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read_command_q <= 1'b0;
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end else begin
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done <= 1'b0;
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read_valid <= 1'b0;
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if (!busy) begin
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mdc <= 1'b0;
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div_count <= '0;
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if (start) begin
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busy <= 1'b1;
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bit_index <= 6'd63;
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read_shift <= 16'd0;
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read_command_q <= !command_write;
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frame_bits[63:32] <= 32'hffffffff;
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frame_bits[31:30] <= 2'b01;
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frame_bits[29:28] <= command_write ? 2'b01 : 2'b10;
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frame_bits[27:23] <= phy_address;
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frame_bits[22:18] <= register_address;
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frame_bits[17:16] <= 2'b10;
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frame_bits[15:0] <= write_data;
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end
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end else if (div_count == MDC_DIV-1) begin
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div_count <= '0;
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if (!mdc) begin
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// Rising MDC: PHY sources read data; master samples it.
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mdc <= 1'b1;
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if (read_command_q && bit_index <= 6'd15)
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read_shift <= {read_shift[14:0], mdio_i};
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end else begin
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// Falling MDC: move to the next bit or finish the command.
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mdc <= 1'b0;
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if (bit_index == 6'd0) begin
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busy <= 1'b0;
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done <= 1'b1;
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if (read_command_q) begin
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read_data <= read_shift;
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read_valid <= 1'b1;
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end
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end else bit_index <= bit_index - 6'd1;
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end
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end else div_count <= div_count + {{(DIV_W-1){1'b0}},1'b1};
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end
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end
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endmodule
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`default_nettype wire
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