onur
3.2 KiB
Digilent Genesys 2 target
This directory contains only the Genesys 2 adaptation of the MAX2771 recorder.
The protocol/capture/FIFO/MAC RTL comes from ../../rtl/common; no portable
module is copied here.
Target-specific files
| File | Function |
|---|---|
rtl/max2771_recorder_top.sv |
connects common blocks, status counters and LEDs |
rtl/ethernet_clock_gen_xilinx.sv |
200 MHz differential input and primitive MMCM for 125 MHz/125 MHz +90° |
rtl/rgmii_tx_xilinx.sv |
Kintex-7 ODDR implementation for TXD/TXCTL/TXC |
rtl/phy_init_rtl8211e.sv |
polls Genesys RTL8211E PHY address 1 and gates 1000/full link |
constraints/genesys2_max2771_recorder.xdc |
verified clock, JA, Ethernet and LED pins |
scripts/build_vivado.tcl |
in-memory/non-project synthesis, P&R, reports and bitstream |
scripts/program_fpga.tcl |
volatile JTAG configuration |
Wiring
| Signal | FPGA ball | JA pin | Standard |
|---|---|---|---|
rf_clk_pmod |
U27 | JA[0] | LVCMOS33 |
rf_data_pmod[0] |
U28 | JA[1] | LVCMOS33 |
rf_data_pmod[1] |
T26 | JA[2] | LVCMOS33 |
rf_data_pmod[2] |
T27 | JA[3] | LVCMOS33 |
rf_data_pmod[3] |
T22 | JA[4] | LVCMOS33 |
Connect a common ground and use only a 3.3-V-compatible digital source.
Simulation
From the repository root:
make genesys2-sim
This runs the common FIFO/protocol/MAC regression. Xilinx primitives are
guarded by SYNTHESIS, so vendor simulation libraries are not required for the
common regression.
Build
make genesys2-build
Equivalent direct command:
vivado -mode batch -source targets/genesys2/scripts/build_vivado.tcl
Output:
build/genesys2/vivado/max2771_recorder.bit
build/genesys2/reports/
The build uses part xc7k325tffg900-2, top max2771_recorder_top, creates an
in-memory project, fails on negative setup/hold slack or unexpected major CDC
warnings and uses no block design or generated IP. A clean Vivado 2026.1 build
on 1 August 2026 completed synthesis, placement, routing, DRC and bitstream
generation with +0.212 ns worst setup slack and +0.090 ns worst hold slack.
Programming
Connect the Digilent JTAG USB port and run:
make genesys2-program
This configures the FPGA volatile SRAM. It does not write configuration flash. Power cycling removes the design.
Clocking and RGMII
The 200 MHz differential oscillator drives an MMCM with a 1000 MHz VCO. It generates 125 MHz at 0° for the MAC/data ODDRs and 125 MHz at +90° for the TXC ODDR. The resulting nominal +2 ns clock shift is required because the board straps RTL8211E transmit delay off.
PHY reset remains asserted for 10 ms, register access waits another 30 ms, and transmit starts only after PHY-specific status reports resolved 1000 Mb/s/full duplex link. Ethernet receive is not implemented.
LEDs
| LED | Meaning |
|---|---|
| 0 | MMCM locked/system ready |
| 1 | qualified 1000/full link |
| 2 | RF sample activity |
| 3 | FIFO non-empty |
| 4 | sample loss/overflow latched |
| 5 | frame activity |
| 6 | first PHY status read completed |
| 7 | Ethernet-domain heartbeat |
See hardware assumptions and timing constraints before hardware sign-off.