onur
24 lines
701 B
Systemverilog
24 lines
701 B
Systemverilog
`default_nettype none
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// One reflected Ethernet CRC-32 byte update. Initialize crc_in to 0xffffffff,
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// update over destination MAC through padding, then transmit ~crc in low-byte
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// first order. Polynomial x^32+x^26+x^23+...+1 is 0xedb88320 reflected.
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module ethernet_crc32 (
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input wire logic [31:0] crc_in,
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input wire logic [7:0] data_in,
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output logic [31:0] crc_out
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);
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integer i;
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logic [31:0] c;
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always_comb begin
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c = crc_in;
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for (i = 0; i < 8; i = i + 1) begin
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if (c[0] ^ data_in[i]) c = (c >> 1) ^ 32'hedb88320;
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else c = (c >> 1);
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end
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crc_out = c;
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end
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endmodule
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`default_nettype wire
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