onur
39 lines
1.1 KiB
Systemverilog
39 lines
1.1 KiB
Systemverilog
`default_nettype none
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// Toggle-based pulse crossing. Pulses must be separated by at least two
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// destination clock cycles. Assertion is asynchronous only at the synchronizer.
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module pulse_sync (
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input wire logic src_clk,
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input wire logic src_rst,
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input wire logic src_pulse,
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input wire logic dst_clk,
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input wire logic dst_rst,
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output logic dst_pulse
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);
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logic src_toggle;
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(* ASYNC_REG = "TRUE" *) logic dst_sync1;
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(* ASYNC_REG = "TRUE" *) logic dst_sync2;
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logic dst_sync2_d;
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always_ff @(posedge src_clk) begin
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if (src_rst) src_toggle <= 1'b0;
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else if (src_pulse) src_toggle <= ~src_toggle;
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end
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always_ff @(posedge dst_clk) begin
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if (dst_rst) begin
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dst_sync1 <= 1'b0;
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dst_sync2 <= 1'b0;
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dst_sync2_d <= 1'b0;
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dst_pulse <= 1'b0;
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end else begin
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dst_sync1 <= src_toggle;
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dst_sync2 <= dst_sync1;
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dst_sync2_d <= dst_sync2;
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dst_pulse <= dst_sync2 ^ dst_sync2_d;
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end
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end
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endmodule
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`default_nettype wire
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