max2771-raw-ethernet-recorder/targets/genesys2/docs/hardware_assumptions.md

Hardware information and assumptions

Verified board information

The pin source is Digilent's official Genesys-2-Master.xdc, commit 00a3404901f35aa9567b01ecb3f2c233b6efe9f4. The official board definition names part xc7k325tffg900-2 and the system oscillator as 200 MHz. The Genesys 2 reference manual identifies the PHY as RTL8211E-VL.

Function	FPGA pin	Standard	Notes
sysclk_p/n	AD12 / AD11	LVDS	200 MHz differential oscillator
cpu_resetn	R19	LVCMOS33	active-low board reset
MDC / MDIO	AF12 / AG12	LVCMOS15	PHY address strapped to 1
RGMII TXC	AE10	LVCMOS15	Bank 33, 1.5 V
RGMII TXD[0:3]	AJ12, AK11, AJ11, AK10	LVCMOS15	in vector order
RGMII TXCTL	AK14	LVCMOS15	no TX error is generated
PHY reset	AH24	LVCMOS33	active low
PHY INTB / PMEB	AK16 / AK15	LVCMOS18	open-drain; not used by this design
RGMII RXC	AG10	LVCMOS15	receive path not implemented
RGMII RXCTL	AH11	LVCMOS15	receive path not implemented
RGMII RXD[0:3]	AJ14, AH14, AK13, AJ13	LVCMOS15	receive path not implemented
LEDs[0:7]	T28, V19, U30, U29, V20, V26, W24, W23	LVCMOS33	user status LEDs

The reference manual states that the board straps auto-negotiation on, advertises 10/100/1000 modes, selects PHY address 00001, and selects no PHY-internal RGMII RX or TX delay. It also shows a 25 MHz PHY crystal; the FPGA does not supply the PHY reference clock.

The RTL8211E datasheet requires PHYRSTB low for at least 10 ms and a further 30 ms before register access. The RTL implements both intervals. Link gating polls PHY-specific status register 0x11; transmit is enabled only when bits [15:14]=10 (1000 Mb/s), bit 13 (full duplex), bit 11 (resolved), and bit 10 (real-time link) are all set.

Assumptions from the specification

• rf_clk_pmod is nominally 32.736 MHz.
• A four-bit word is valid on every configured sampling edge.
• Default capture is rising-edge and default packing is earlier-sample-high-nibble.
• JA is a 3.3 V interface and the MAX2771-side signals presented to JA are electrically compatible with LVCMOS33.
• Ethernet destination is broadcast and source is the fixed locally administered address 02:27:71:00:00:01.

MAX2771 datasheet confirmation required

• Confirm the selected MAX2771 digital-output mode really produces one complete four-bit word per RF clock edge.
• Confirm output voltage, drive strength, clock polarity, setup, hold, and clock-to-output limits for the exact supply and load.
• Confirm whether the default rising capture edge is the center of the valid data eye. Change CAPTURE_RISING only after that check.
• Confirm whether the four bits represent the desired channel/order. RTL records [3:0] literally and deliberately does not reinterpret it.

Measurement required

• Measure MAX2771 clock-to-data timing at the Genesys 2 JA pins, including cable/adapter skew. Put the resulting min/max values into the commented set_input_delay commands in the XDC.
• Measure the four data-line skews if wiring is not length matched.
• Verify the forwarded RGMII TX clock is centered approximately 2.0 ns after TXD/TXCTL transitions at the PHY pins. The MMCM provides the nominal shift; board trace and I/O delay still deserve hardware measurement.
• Confirm clean 3.3 V levels, ground return, edge quality, and absence of overshoot at JA before long captures.

No unverified board pin has been inserted into the constraints.