max2771-raw-ethernet-recorder/targets/genesys2/docs/timing_constraints.md

Timing constraints and closure

Clock plan

Clock	Source	Frequency / period	Use
sys_clk_200	AD12/AD11 LVDS oscillator	200 MHz / 5.000 ns	MMCM input
clk125_i	MMCM VCO 1000 MHz, divide 8	125 MHz / 8.000 ns, 0°	packetizer, MAC, MDIO, RGMII data ODDR
clk125_90_i	same MMCM output divide	125 MHz / 8.000 ns, +90°	forwarded RGMII TXC ODDR
rgmii_txc	ODDR from clk125_90_i	125 MHz, +2.000 ns	PHY source-synchronous clock
mdio_mdc	counter from 125 MHz	2.5 MHz	Clause-22 management
rf_sample_clk	U27	32.736 MHz / 30.547 ns	MAX2771 capture and FIFO write

The RTL8211E is strapped with TX delay disabled. Therefore the FPGA creates RGMII-ID source-clock skew: GMII/RGMII data changes from ODDRs clocked at 0°, and TXC changes from an ODDR clocked at +90°. At 125 MHz, 90° is 2.000 ns. RGMII TX output delays use the standard 1.0 ns setup/1.0 ns hold receive budget around that centered clock edge.

CDC exceptions

The RF and Ethernet clocks are asynchronous. The only crossings are:

• FIFO write/read Gray pointers, each through two ASYNC_REG stages;
• the Gray-coded cumulative drop counter, through two ASYNC_REG stages;
• a toggle-based sample-activity indicator, through two ASYNC_REG stages;
• reset synchronizers with asynchronous assertion and synchronous deassertion.

The XDC asynchronous clock grouping is valid because no ordinary data/control logic crosses those groups. The multi-bit FIFO data is stored in true dual-clock block RAM and is read only under synchronized pointer control; it is not sampled as a combinational bus crossing.

Vivado reports CDC-6 for the three intentionally Gray-coded buses even when it recognizes their two ASYNC_REG stages. The build script accepts only named FIFO/drop-counter instances and fails for any other Warning or Critical CDC object.

MAX2771 input delay boundary

The clock is constrained to 30.547 ns and the input registers are forced into IOBs. The project does not claim RF input setup/hold sign-off yet: neither the task input nor the Genesys 2 documentation provides MAX2771 tCO, cable delay, or inter-bit skew. The XDC contains conspicuous placeholder commands rather than fabricated numbers.

Before hardware sign-off:

1. derive earliest/latest data arrival at each FPGA pin from the MAX2771 datasheet;
2. add measured cable/adapter and bit-to-bit skew;
3. replace the placeholder max/min values in the XDC;
4. rerun make genesys2-build and inspect build/genesys2/reports/timing_post_route.rpt;
5. verify the eye with an oscilloscope or logic analyzer at JA.

The current 2026.1 build routes successfully with setup WNS +0.212 ns and hold WNS +0.090 ns for constrained paths. These numbers do not replace the missing external RF input-delay model.