onur
86 lines
3.5 KiB
Systemverilog
86 lines
3.5 KiB
Systemverilog
`default_nettype none
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// The Genesys 2 straps the RTL8211E-VL for auto-negotiation and PHY address 1.
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// After the mandatory post-reset settling time, this controller polls PHYSR
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// (register 0x11) and permits transmit only for resolved 1000 Mb/s full duplex.
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module phy_init #(
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parameter int unsigned CLK_HZ = 125_000_000,
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parameter int unsigned SETTLE_MS = 30,
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parameter int unsigned POLL_MS = 100
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) (
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input wire logic clk,
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input wire logic rst,
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input wire logic phy_reset_complete,
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output logic mdio_start,
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output logic mdio_write,
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output logic [4:0] mdio_phy_address,
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output logic [4:0] mdio_register_address,
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output logic [15:0] mdio_write_data,
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input wire logic mdio_busy,
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input wire logic mdio_done,
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input wire logic [15:0] mdio_read_data,
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output logic initialization_complete,
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output logic link_ready,
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output logic [63:0] link_down_events
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);
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localparam longint unsigned SETTLE_CYCLES = (CLK_HZ / 1000) * SETTLE_MS;
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localparam longint unsigned POLL_CYCLES = (CLK_HZ / 1000) * POLL_MS;
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localparam int unsigned TIMER_W = $clog2(((POLL_CYCLES > SETTLE_CYCLES) ? POLL_CYCLES : SETTLE_CYCLES) + 1);
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typedef enum logic [2:0] {I_WAIT_RESET, I_SETTLE, I_START, I_WAIT_MDIO, I_POLL_WAIT} istate_t;
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istate_t state;
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logic [TIMER_W-1:0] timer;
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logic new_link_ready;
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always_comb begin
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mdio_write = 1'b0;
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mdio_phy_address = 5'd1;
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mdio_register_address = 5'h11;
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mdio_write_data = 16'd0;
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new_link_ready = (mdio_read_data[15:14] == 2'b10) &&
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mdio_read_data[13] && mdio_read_data[11] && mdio_read_data[10];
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end
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always_ff @(posedge clk) begin
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if (rst) begin
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state <= I_WAIT_RESET;
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timer <= '0;
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mdio_start <= 1'b0;
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initialization_complete <= 1'b0;
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link_ready <= 1'b0;
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link_down_events <= 64'd0;
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end else begin
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mdio_start <= 1'b0;
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case (state)
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I_WAIT_RESET: begin
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link_ready <= 1'b0;
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if (phy_reset_complete) begin timer <= '0; state <= I_SETTLE; end
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end
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I_SETTLE: begin
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if (timer == SETTLE_CYCLES-1) begin timer <= '0; state <= I_START; end
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else timer <= timer + {{(TIMER_W-1){1'b0}},1'b1};
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end
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I_START: begin
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if (!mdio_busy) begin mdio_start <= 1'b1; state <= I_WAIT_MDIO; end
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end
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I_WAIT_MDIO: begin
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if (mdio_done) begin
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initialization_complete <= 1'b1;
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if (link_ready && !new_link_ready)
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link_down_events <= link_down_events + 64'd1;
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link_ready <= new_link_ready;
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timer <= '0;
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state <= I_POLL_WAIT;
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end
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end
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I_POLL_WAIT: begin
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if (timer == POLL_CYCLES-1) begin timer <= '0; state <= I_START; end
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else timer <= timer + {{(TIMER_W-1){1'b0}},1'b1};
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end
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default: state <= I_WAIT_RESET;
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endcase
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end
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end
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endmodule
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`default_nettype wire
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