onur
104 lines
3.4 KiB
Systemverilog
104 lines
3.4 KiB
Systemverilog
`timescale 1ns/1ps
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`default_nettype none
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module tb_async_fifo_gray;
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localparam int DEPTH = 16;
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logic w_clk=0, r_clk=0, w_rst=1, r_rst=1;
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logic w_en=0, r_en=0;
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logic [15:0] w_data=0, r_data;
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logic w_full, r_empty, r_valid;
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logic [$clog2(DEPTH):0] w_level, r_level;
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logic [63:0] overflow_count, underflow_count;
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logic [15:0] expected [0:20000];
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integer writes=0, reads=0, errors=0;
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integer cycles;
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always #3.5 w_clk = ~w_clk;
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always #5.5 r_clk = ~r_clk;
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async_fifo_gray #(.DATA_WIDTH(16), .DEPTH(DEPTH)) dut (
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.w_clk(w_clk), .w_rst(w_rst), .w_en(w_en), .w_data(w_data),
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.w_full(w_full), .w_level(w_level), .overflow_attempt_count(overflow_count),
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.r_clk(r_clk), .r_rst(r_rst), .r_en(r_en), .r_data(r_data),
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.r_valid(r_valid), .r_empty(r_empty), .r_level(r_level),
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.underflow_attempt_count(underflow_count)
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);
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always @(posedge w_clk) begin
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if (!w_rst && w_en && !w_full) begin
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expected[writes] = w_data;
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writes = writes + 1;
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end
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end
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always @(posedge r_clk) begin
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if (!r_rst && r_valid) begin
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if (r_data !== expected[reads]) begin
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$error("FIFO mismatch at read %0d: got %04x expected %04x", reads, r_data, expected[reads]);
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errors = errors + 1;
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end
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reads = reads + 1;
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end
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end
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initial begin
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repeat (4) @(posedge w_clk);
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w_rst = 0;
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repeat (3) @(posedge r_clk);
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r_rst = 0;
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// Fill through the full boundary and intentionally attempt overflow.
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@(negedge w_clk); w_en=1;
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repeat (DEPTH+8) begin
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@(negedge w_clk); w_data = w_data + 16'd1;
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end
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@(negedge w_clk); w_en=0;
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if (!w_full) $fatal(1, "FIFO did not assert full");
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// Drain through empty and intentionally attempt underflow.
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@(negedge r_clk); r_en=1;
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repeat (DEPTH+12) @(negedge r_clk);
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@(negedge r_clk); r_en=0;
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repeat (4) @(posedge r_clk);
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if (!r_empty) $fatal(1, "FIFO did not assert empty");
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// Random unrelated-clock traffic for wrap-around and simultaneous use.
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fork
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begin
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for (cycles=0; cycles<5000; cycles=cycles+1) begin
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@(negedge w_clk);
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w_en = ($urandom_range(0,99) < 68);
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w_data = w_data + 16'd1;
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end
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@(negedge w_clk); w_en=0;
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end
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begin
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repeat (5000) begin
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@(negedge r_clk);
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r_en = ($urandom_range(0,99) < 54);
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end
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@(negedge r_clk); r_en=0;
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end
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join
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// Final drain.
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r_en=1;
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while (reads < writes) @(negedge r_clk);
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r_en=0;
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repeat (4) @(posedge r_clk);
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if (errors != 0) $fatal(1, "FIFO scoreboard saw %0d errors", errors);
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if (overflow_count == 0) $fatal(1, "overflow attempt counter stayed zero");
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if (underflow_count == 0) $fatal(1, "underflow attempt counter stayed zero");
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if (reads != writes) $fatal(1, "writes=%0d reads=%0d", writes, reads);
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$display("PASS tb_async_fifo_gray: %0d ordered words, overflow=%0d underflow=%0d",
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reads, overflow_count, underflow_count);
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$finish;
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end
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initial begin
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#500000;
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$fatal(1, "FIFO test timeout");
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end
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endmodule
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`default_nettype wire
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