onur
50 lines
2.0 KiB
Systemverilog
50 lines
2.0 KiB
Systemverilog
`timescale 1ns/1ps
|
|
`default_nettype none
|
|
|
|
module tb_capture_overflow;
|
|
localparam int DEPTH=16;
|
|
logic rf_clk=0, r_clk=0, rst=1;
|
|
logic [3:0] rf_data=0;
|
|
logic fifo_clk,w_en,w_full,r_en=0,r_valid,r_empty;
|
|
logic [68:0] w_data,r_data;
|
|
logic [$clog2(DEPTH):0] wl,rl;
|
|
logic [63:0] seen,captured,dropped,ovf,udf;
|
|
logic loss,activity;
|
|
integer i,read_count=0;
|
|
always #15.2735 rf_clk=~rf_clk;
|
|
always #4 r_clk=~r_clk;
|
|
|
|
max2771_capture cap(.rf_clk_pmod(rf_clk),.rst(rst),.rf_data_pmod(rf_data),
|
|
.fifo_full(w_full),.fifo_w_clk(fifo_clk),.fifo_w_en(w_en),.fifo_w_data(w_data),
|
|
.samples_seen(seen),.samples_captured(captured),.samples_dropped(dropped),
|
|
.loss_latched(loss),.sample_activity_pulse(activity));
|
|
async_fifo_gray #(.DATA_WIDTH(69),.DEPTH(DEPTH)) fifo(
|
|
.w_clk(fifo_clk),.w_rst(rst),.w_en(w_en),.w_data(w_data),.w_full(w_full),
|
|
.w_level(wl),.overflow_attempt_count(ovf),.r_clk(r_clk),.r_rst(rst),
|
|
.r_en(r_en),.r_data(r_data),.r_valid(r_valid),.r_empty(r_empty),
|
|
.r_level(rl),.underflow_attempt_count(udf));
|
|
|
|
always @(posedge r_clk) if(r_valid) begin
|
|
if(r_data[67:4]!==read_count || r_data[3:0]!==((read_count+1)&15))
|
|
$fatal(1,"overwrite/order failure read=%0d entry index=%0d data=%x",read_count,r_data[67:4],r_data[3:0]);
|
|
read_count=read_count+1;
|
|
end
|
|
|
|
initial begin
|
|
repeat(3) @(posedge rf_clk); rst=0;
|
|
for(i=0;i<48;i=i+1) begin @(negedge rf_clk); rf_data=(i+1)&15; end
|
|
@(posedge rf_clk); #1;
|
|
if(!loss || dropped==0 || ovf==0 || dropped!==ovf)
|
|
$fatal(1,"overflow status failure loss=%b dropped=%0d attempts=%0d",loss,dropped,ovf);
|
|
r_en=1;
|
|
wait(read_count==DEPTH);
|
|
r_en=0;
|
|
if(captured<DEPTH) $fatal(1,"captured count %0d smaller than FIFO depth",captured);
|
|
$display("PASS tb_capture_overflow: no overwrite, dropped=%0d and loss latched",dropped);
|
|
$finish;
|
|
end
|
|
initial begin #100000; $fatal(1,"capture overflow timeout"); end
|
|
endmodule
|
|
|
|
`default_nettype wire
|